Patents by Inventor Darryl J. Becker

Darryl J. Becker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9887847
    Abstract: A conductor on glass security layer may be located within a printed circuit board (PCB) of a crypto adapter card or within a daughter card upon the crypto adapter card. The conductor on glass security layer includes a glass dielectric layer that remains intact in the absence of point force loading and shatters when a point load punctures or otherwise contacts the glass dielectric layer. The conductor on glass security layer also includes a conductive security trace upon the glass dielectric layer. A physical access attempt shatters a majority of the glass dielectric layer, which in turn fractures the security trace. A monitoring circuit that monitors the resistance of the conductive security trace detects the resultant open circuit or change in security trace resistance and initiates a tamper signal that which may be received by one or more computer system devices to respond to the unauthorized attempt of physical access.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, Darryl J. Becker, Matthew S. Doyle, Mark J. Jeanson, Mark O. Maxson
  • Patent number: 9887840
    Abstract: A bus communicates bits in parallel between a transmitter and receiver. A selected set of bits has its bits scrambled. Scrambling the bits includes assigning two or more bits of the selected set of bits to atypical lanes of the bus. By scrambling the bits, the order in which the bits of the selected set of bits are ready by a processer are obscured. The set of bits is transmitted to the receiver with one or more delays. The delays are on one or more of the lanes of the bus. The delays indicate the order of the bits. The receiver is configured to use the delays to identify the order of the bits and unscramble the set of bits.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, Darryl J. Becker, Matthew S. Doyle, Mark O. Maxson
  • Publication number: 20170279532
    Abstract: An optical electromagnetic radiation (EM) emitter and receiver are located upon a printed circuit board (PCB) glass security layer. A predetermined reference flux or interference pattern, respectively, is an expected flux or reflection pattern of EM emitted from the EM emitter, transmitted by the glass security layer, and received by the EM receiver. When the PCB is subject to an unauthorized access thereof the optical EM transmitted by glass security layer is altered. An optical monitoring device that monitors the flux or interference pattern of the optical EM received by the EM receiver detects a change in flux or interference pattern, in relation to the reference flux or reference interference pattern, respectively, and passes a tamper signal to one or more computer system devices to respond to the unauthorized access. For example, one or more cryptographic adapter card or computer system functions or secured crypto components may be disabled.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 28, 2017
    Inventors: Gerald K. Bartley, Darryl J. Becker, Matthew S. Doyle, Mark J. Jeanson, Mark O. Maxson
  • Publication number: 20170244756
    Abstract: A security matrix layer between a first and second conductive shorting layers are located within a printed circuit board (PCB) that carries out cryptographic data handling functions. The security matrix layer includes at least two microcapsules each containing one or more reactants. When the security matrix layer is accessed, drilled, or otherwise damaged, the microcapsules rupture and the reactants react to form at least an electrically conductive material. The electrically conductive material contacts and shorts the first and second conductive shorting layers. A monitoring device that monitors whether the first and second conductive shorting layers have shorted detects the short and passes a tamper signal that is received by one or more computer system devices to respond to the unauthorized physical access attempt.
    Type: Application
    Filed: February 19, 2016
    Publication date: August 24, 2017
    Inventors: Gerald K. Bartley, Darryl J. Becker, Matthew S. Doyle, Joseph Kuczynski, Timothy J. Tofil
  • Patent number: 9739825
    Abstract: A stub of a via formed in a printed circuit board is backdrilled to a predetermined depth. A capacitance probe is positioned within the via. Then the capacitance probe is used to obtain a test capacitance measurement. The test capacitance measurement is compared to a predetermined baseline capacitance measurement. Residual conductive plating material in the backdrilled stub causes the test capacitance measurement to exceed the predetermined baseline capacitance measurement. An indication is made that the predetermined baseline capacitance measurement has been exceeded.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, Darryl J. Becker, Matthew S. Doyle, Philip R. Germann, Mark O. Maxson
  • Publication number: 20170222816
    Abstract: A conductor on glass security layer may be located within a printed circuit board (PCB) of a crypto adapter card or within a daughter card upon the crypto adapter card. The conductor on glass security layer includes a glass dielectric layer that remains intact in the absence of point force loading and shatters when a point load punctures or otherwise contacts the glass dielectric layer. The conductor on glass security layer also includes a conductive security trace upon the glass dielectric layer. A physical access attempt shatters a majority of the glass dielectric layer, which in turn fractures the security trace. A monitoring circuit that monitors the resistance of the conductive security trace detects the resultant open circuit or change in security trace resistance and initiates a tamper signal that which may be received by one or more computer system devices to respond to the unauthorized attempt of physical access.
    Type: Application
    Filed: February 3, 2016
    Publication date: August 3, 2017
    Inventors: Gerald K. Bartley, Darryl J. Becker, Matthew S. Doyle, Mark J. Jeanson, Mark O. Maxson
  • Publication number: 20170194726
    Abstract: Disclosed aspects relate to connector structures and a card. A first connector structure is to join a first subset of a set of electrical connections. A second connector structure is to join a second subset of the set of electrical connections. The card manages the set of electrical connections and is located between the first and second connector structures to connect with the first and second connector structures.
    Type: Application
    Filed: January 4, 2016
    Publication date: July 6, 2017
    Inventors: Gerald K. Bartley, Darryl J. Becker, Matthew S. Doyle, Mark J. Jeanson, Mark O. Maxson
  • Publication number: 20170168984
    Abstract: A lane within a processor bus that communicatively connects a transmitter and a receiver is dynamically assigned as a clock lane. The clock lane subsequently transmits a reference clock signal to coordinate data communications from the transmitter to the receiver. The clock lane may be assigned by determining signal margins of various lanes of the processor bus. The signal margins are determined by the transmitter sending a test pattern upon the various lanes and analyzing the received test pattern at the receiver. A dynamically assigned clock lane results increased overall signal integrity of communications between the transmitter and receiver. Further, a dynamically assigned clock lane may result in different lanes being assigned as the clock lane at distinct boot up instances, adding to the complexity of the unauthorized user determining the operational logic of the transmitter.
    Type: Application
    Filed: March 4, 2016
    Publication date: June 15, 2017
    Inventors: Gerald K. Bartley, Darryl J. Becker, Matthew S. Doyle, Mark J. Jeanson, Mark O. Maxson
  • Publication number: 20170168983
    Abstract: A lane within a processor bus that communicatively connects a transmitter and a receiver is dynamically assigned as a clock lane. The clock lane subsequently transmits a reference clock signal to coordinate data communications from the transmitter to the receiver. The clock lane may be assigned by determining signal margins of various lanes of the processor bus. The signal margins are determined by the transmitter sending a test pattern upon the various lanes and analyzing the received test pattern at the receiver. A dynamically assigned clock lane results increased overall signal integrity of communications between the transmitter and receiver. Further, a dynamically assigned clock lane may result in different lanes being assigned as the clock lane at distinct boot up instances, adding to the complexity of the unauthorized user determining the operational logic of the transmitter.
    Type: Application
    Filed: December 14, 2015
    Publication date: June 15, 2017
    Inventors: Gerald K. Bartley, Darryl J. Becker, Matthew S. Doyle, Mark J. Jeanson, Mark O. Maxson
  • Patent number: 9680477
    Abstract: Systems and methods to obstruct analysis of a microchip may include an electrical component of a microchip and a photodetector positioned within the microchip. The photodetector may be configured to sense electromagnetic radiation. Circuitry in electrical communication with the photodetector may be configured to initiate an action to obstruct analysis of the electrical component in response to a change in a level of the electromagnetic radiation.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: June 13, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerald K. Bartley, Darryl J. Becker, Matthew S. Doyle, Mark O. Maxson
  • Patent number: 9665736
    Abstract: Systems and methods to safeguard data and hardware may include a memory configured to store a first image and sensitive data, and an optical sensor configured to capture a second image. A sensor signal comprising the captured second image may be generated. A controller having access to the memory may be configured to receive the sensor signal. The controller may be further configured to compare the stored first image to the captured second image, and based on the comparison, to determine whether the sensitive data is accessed.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: May 30, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerald K. Bartley, Darryl J. Becker, Matthew S. Doyle, Mark O. Maxson
  • Patent number: 9665797
    Abstract: Aspects of the present disclosure are directed towards environmental based location monitoring. Environmental based location monitoring can include collecting, a first set of image data that corresponds to a first set of environmental characteristics existing within a bounded area encompassing a hardware element of the computer and determining an environmental difference based on a difference between a first location corresponding to a geographic position of the hardware element relative to the first set of environmental characteristics and a second location corresponding to an approved geographic position of the hardware element. Environmental based location monitoring can include determining that the environmental difference does not satisfy a threshold and executing a reaction sequence in the computer, in response to determining that the environmental difference does not satisfy the threshold.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: May 30, 2017
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, Darryl J. Becker, Matthew S. Doyle, Mark O. Maxson
  • Patent number: 9652636
    Abstract: Aspects of the present disclosure are directed towards a method of electronic verification of motion data. This includes collecting a first set of motion data that corresponds to a first set of motion characteristics generated from physically moving a hardware element of a computer ending upon inserting the hardware element of the computer into a computer chassis. This can further include determining an approved set of motion data and comparing the first set of motion data to the approved set of motion data. This can further include determining a difference between the first set of motion data and the approved set of motion data. This can further include determining that the difference does not satisfy a threshold. This can further include executing a reaction sequence in the computer, in response to determining that the difference does not satisfy the threshold.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: May 16, 2017
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, Darryl J. Becker, Matthew S. Doyle, Mark O. Maxson
  • Publication number: 20170105533
    Abstract: A removable backrest is attached to a cooler in such a manner that does not interfere with the opening or closing of the lid nor does it interfere with the sealing mechanism of the cooler. The removable backrest inserts into existing slots positioned in the walls of certain commercially available coolers. The angle of the frame permits a user to sit on the complete lid of the cooler and lean against the backrest. While the backrest is in position, the lid may be opened or closed at the user's convenience.
    Type: Application
    Filed: November 2, 2016
    Publication date: April 20, 2017
    Inventors: Darryl J. Becker, Mike Bishop
  • Publication number: 20170105532
    Abstract: A removable backrest is attached to a cooler in such a manner that does not interfere with the opening or closing of the lid nor does it interfere with the sealing mechanism of the cooler. The removable backrest inserts into existing slots positioned in the walls of certain commercially available coolers. The angle of the frame permits a user to sit on the complete lid of the cooler and lean against the backrest. While the backrest is in position, the lid may be opened or closed at the user's convenience.
    Type: Application
    Filed: June 24, 2016
    Publication date: April 20, 2017
    Inventors: Darryl J. Becker, Mike Bishop
  • Patent number: 9612988
    Abstract: A device uses donor circuit blocks in a donor integrated circuit to replace defective circuit blocks in a recipient integrated circuit and create a functional integrated circuit. The recipient integrated circuit has a first number of cores, the first number including a recipient core, and the recipient core having a recipient circuit block, a switching element, and a recipient communication point, the first number of cores connected by a data bus. The recipient core has an intended function. The donor integrated circuit has a second number of cores, the second number smaller than the first number. The second number includes a donor core having a donor communication point electrically connected to a donor circuit block, the donor circuit block having the intended function. The recipient connection point is electrically connected to the donor connection point and the switching element switched to disable the recipient circuit block in the recipient core.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: April 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, Darryl J. Becker, Philip R. Germann, William P. Hovis
  • Publication number: 20170093568
    Abstract: A bus communicates bits in parallel between a transmitter and receiver. A selected set of bits has its bits scrambled. Scrambling the bits includes assigning two or more bits of the selected set of bits to atypical lanes of the bus. By scrambling the bits, the order in which the bits of the selected set of bits are ready by a processer are obscured. The set of bits is transmitted to the receiver with one or more delays. The delays are on one or more of the lanes of the bus. The delays indicate the order of the bits. The receiver is configured to use the delays to identify the order of the bits and unscramble the set of bits.
    Type: Application
    Filed: September 29, 2015
    Publication date: March 30, 2017
    Inventors: Gerald K. Bartley, Darryl J. Becker, Matthew S. Doyle, Mark O. Maxson
  • Patent number: 9569644
    Abstract: Aspects of the present disclosure are directed towards a method of electronic verification of motion data. This includes collecting a first set of motion data that corresponds to a first set of motion characteristics generated from physically moving a hardware element of a computer ending upon inserting the hardware element of the computer into a computer chassis. This can further include determining an approved set of motion data and comparing the first set of motion data to the approved set of motion data. This can further include determining a difference between the first set of motion data and the approved set of motion data. This can further include determining that the difference does not satisfy a threshold. This can further include executing a reaction sequence in the computer, in response to determining that the difference does not satisfy the threshold.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, Darryl J. Becker, Matthew S. Doyle, Mark O. Maxson
  • Patent number: 9568940
    Abstract: An integrated circuit (IC) stack device for multiple active vertically stacked cores is disclosed. The IC stack device can include a primary IC having a first set of cores, and a supplementary IC interfaced with the primary IC having a second set of cores. The IC stack device can also include a peripheral component connection located such that the primary IC is between the peripheral component connection and the supplemental IC. The IC stack device can include control logic configured to route, in a primary mode, signals from a particular core of the first set of cores to a data bus. The control logic can route, in a secondary mode, signals from a particular core of the second set of cores to a data bus. The control logic can route, in a dual mode, signals from both of the particular cores to a data bus.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, Darryl J. Becker, William P. Hovis
  • Publication number: 20170039391
    Abstract: Systems and methods to safeguard data and hardware may include a memory configured to store a first image and sensitive data, and an optical sensor configured to capture a second image. A sensor signal comprising the captured second image may be generated. A controller having access to the memory may be configured to receive the sensor signal. The controller may be further configured to compare the stored first image to the captured second image, and based on the comparison, to determine whether the sensitive data is accessed.
    Type: Application
    Filed: December 18, 2014
    Publication date: February 9, 2017
    Inventors: Gerald K. Bartley, Darryl J. Becker, Matthew S. Doyle, Mark Owen Maxson