Abstract: Examples of synchronization of a gyroscope in a virtual-reality (VR) environment are described. In some examples, gyroscopic feedback for VR application content may be predicted. In some examples, a time shift corresponding to a physical system lag of a gyroscope may be added to synchronize the gyroscopic feedback with the VR application content. In some examples, the gyroscopic feedback may be applied based on the time shift.

Abstract: An optical system comprises a first optical path configured to supply a first light with a first range of wavelengths; a second optical path configured to supply a second light with a second range of wavelengths shorter than the first range of wavelengths; a third optical path configured to supply a third light with a third range of wavelengths shorter than the second range of wavelengths; an optical I/O unit configured to emit the first light, the second light and the third light to a target and acquire a light from the target; a reference unit configured to split off a reference light from the third light; and a detector that includes a range of detection wavelengths shared with a CARS light and an interference light.

Abstract: A method of on-demand energy delivery to an active suspension system is disclosed. The suspension system includes an actuator body, a hydraulic pump, an electric motor, a plurality of sensors, an energy storage facility, and a controller. The method includes disposing an active suspension system in a vehicle between a wheel mount and a vehicle body, detecting a wheel event requiring control of the active suspension; and sourcing energy from the energy storage facility and delivering it to the electric motor in response to the wheel event.

Abstract: A caching system including a first sub-cache, and a second sub-cache, coupled in parallel with the first cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and wherein the second sub-cache includes: color tag bits configured to store an indication that a corresponding cache line of the second sub-cache storing write miss data is associated with a color tag, and an eviction controller configured to evict cache lines of the second sub-cache storing write-miss data based on the color tag associated with the cache line.

Abstract: Cleaning and/or maintaining operability of sensors, e.g., mounted on vehicles, e.g., autonomously operated vehicles, and systems, methods, and technologies that support the same. The sensor cleaning system can include a first fluid source and a second fluid source, and can also include a plurality of nozzles each coupled to the first fluid source and to the second fluid source and each including an outlet directed at a subset of vehicle sensors. The system can further include a control system with a controller configured to supply a first fluid from the first fluid source to a selected nozzle, or supply a combination of the first fluid from the first fluid source and a second fluid from the second fluid source to a selected nozzle, to thereby clean a subset of sensors. Methods of manufacturing, configuring, and installing such systems are also disclosed.

Abstract: A digital signal processor having a CPU with a program counter register and, optionally, an event context stack pointer register for saving and restoring the event handler context when higher priority event preempts a lower priority event handler. The CPU is configured to use a minimized set of addressing modes that includes using the event context stack pointer register and program counter register to compute an address for storing data in memory. The CPU may also eliminate post-decrement, pre-increment and post-decrement addressing and rely only on post-increment addressing.

Abstract: Methods, apparatus, systems and articles of manufacture to facilitate atomic operation in victim cache are disclosed. An example system includes a first cache storage to store a first set of data; a second cache storage to store a second set of data that has been evicted from the first cache storage; and a storage queue coupled to the first cache storage and the second cache storage, the storage queue including: an arithmetic component to: receive the second set of data from the second cache storage in response to a memory operation; and perform an arithmetic operation on the second set of data to produce a third set of data; and an arbitration manager to store the third set of data in the second cache storage.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to reduce read-modify-write cycles for non-aligned writes. An example apparatus includes a memory that includes a plurality of memory banks, an interface configured to be coupled to a central processing unit, the interface to obtain a write operation from the central processing unit, wherein the write operation is to write a subset of the plurality of memory banks, and bank processing logic coupled to the interface and to the memory, the bank processing logic to determine the subset of the plurality of memory banks to write based on the write operation, and determine whether to cause a read operation to be performed in response to the write operation based on whether a number of addresses in the subset of the plurality of memory banks to write satisfies a threshold.

Abstract: Antimicrobial compositions including at least one acid and at least one anionic surfactant are provided. In particular, food contact antimicrobial compositions including at least one acid and at least one anionic surfactant provide efficacious virucidal activity, including against Norovirus, having acceptable use solution pH that do not require use of personal protective equipment (PPE), are surface compatible and do not leave residues on treated surfaces. Methods of cleaning a surface with the compositions are also provided and may beneficially eliminate the need to rinse the antimicrobial compositions after use.

Abstract: In a lithographic process, product units such as semiconductor wafers are subjected to lithographic patterning operations and chemical and physical processing operations. Alignment data or other measurements are made at stages during the performance of the process to obtain object data representing positional deviation or other parameters measured at points spatially distributed across each unit. This object data is used to obtain diagnostic information by performing a multivariate analysis to decompose a set of vectors representing the units in the multidimensional space into one or more component vectors. Diagnostic information about the industrial process is extracted using the component vectors. The performance of the industrial process for subsequent product units can be controlled based on the extracted diagnostic information.

Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

Abstract: A technique for selectively configuring a case of a handheld device to shield an antenna from receiving or transmitting wireless signals is disclosed. The technique includes moving a blocking element on the case between a first position and a second position. The blocking element is a physical structure that is rotatable, slidable, or removable to switch between the first position and the second position. In response to moving the blocking element to the first position, the blocking element blocks wireless signals received or transmitted by the antenna of the handheld device. In response to moving the blocking element to the second position, wireless signals can be received or transmitted through the case by the antenna.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to evict in a dual datapath victim cache system. An example apparatus includes a cache storage, a cache controller operable to receive a first memory operation and a second memory operation concurrently, comparison logic operable to identify if the first and second memory operations missed in the cache storage, and a replacement policy component operable to, when at least one of the first and second memory operations corresponds to a miss in the cache storage, reserve an entry in the cache storage to evict based on the first and second memory operations.

Abstract: In an example implementation, a method includes receiving, at a computing device, borrower information and requested financing plan information. Likewise, a method includes outputting at least a portion of the received information to a second computing device and, after receiving an indication of a decision denying the requested financing plan, outputting at least a portion of the received information to a computing device associated with a lender and confirming, to a computing device associated with a borrower or a merchant that the information has been sent to the lender.

Abstract: Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.

Abstract: A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing write-memory commands that are not cached in the first sub-cache, the second sub-cache including privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a level of privilege, and wherein the second sub-cache is further configured to receive a first write memory command for a memory address associated with a first level of privilege, store, in the second sub-cache, first data associated with the first write memory command and the level of privilege associated with the cache line, receive a second write memory command for the cache line, the second write memory command associated with a second level of privilege, merge the first level of privilege with the second level of privilege, and output the merged privilege level with the cache line.

Abstract: A print device may include a refill interface, a processor, and a computer readable medium. The refill interface may have an electrical interface for transmission and reception of signals between the print device and a refill container. And the computer-readable medium may have instructions stored thereon that when executed by the processor are to cause the processor to fetch signals, via the electrical interface of the refill interface, from the refill container indicative of a licensed print functionality of the print device. The instructions may also be to enable the licensed print functionality on the print device responsive to the fetched signals and to maintain the licensed print functionality enabled subsequent to detachment of the refill container.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: Methods and systems for controlling a circuit designed to protect electrical equipment, in particular sensitive power grid equipment such as transformers, are disclosed. In particular, methods of local and remote control of operation of protection circuits are provided that allow for remote access to change an operational mode of such protection circuits, while ensuring that power grid equipment is protected locally regardless of any configuration instructions received from a remote or centralized facility. Override levels may be set to ensure power grid transformer protection, regardless of operational mode or remote instruction.

Abstract: A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.