Abstract: The present disclosure relates to atomic quantum and photonic apparatuses and methods, for example, atomic radio apparatuses and methods. The disclosure describes various aspects of atomic radio. More specifically, the disclosure describes an atomic radio apparatus and associated hardware. Methods for performing radio communications, sensing, and imaging, are described. The disclosure further describes laser, optical, photonics, atom-photonics, and hybrid micro-integrated subsystems for Rydberg excitation, spectroscopy, and quantum technology.

Abstract: Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.

Abstract: An extra-cardiovascular implantable cardioverter defibrillator (ICD) having a low voltage therapy module and a high voltage therapy module is configured to select, by a control module of the ICD, a pacing output configuration from at least a low-voltage pacing output configuration of the low voltage therapy module and a high-voltage pacing output configuration of the high voltage therapy module. The high voltage therapy module includes a high voltage capacitor having a first capacitance and the low voltage therapy module includes a plurality of low voltage capacitors each having up to a second capacitance that is less than the first capacitance. The ICD control module controls a respective one of the low voltage therapy module or the high voltage therapy module to deliver extra-cardiovascular pacing pulses in the selected pacing output configuration via extra-cardiovascular electrodes coupled to the ICD.

Abstract: A first flush diverter system, the system comprising an inlet supplying a fluid, a flush chamber comprising an opening through which fluid can pass, a retention chamber for containing a predetermined volume of fluid, and an outlet for conveying overflow fluid. The retention chamber is housed within the flush chamber, the retention chamber comprises a receiving aperture for receiving the fluid, and the retention chamber is configured to engageably seal the opening when the retention chamber contains the predetermined volume of fluid. The first flush diverter system overcomes limitations of flush storage containers, including the requirement to drain said flush storage containers.

Abstract: Provided are food products that have structures, textures, and other properties comparable to those of animal meat, and that may therefore serve as substitutes for animal meat. Also provided are processes for production of such ground meat-like food products.

Abstract: An aqueous based drilling fluid that exhibits improved lubricity, containing a sodium alkylglucosides hydroxypropyl phosphates lubricant component.

Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache management operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for read-modify-write support in multi-banked data RAM cache for bank arbitration. An example data cache system includes a store queue including a plurality of bank queues including a first bank queue having a write and read port configured to receive a respective write and read operation, storage coupled to the store queue including a plurality of data banks including a first data bank having a first port configured to receive the write or the read operation, first through third multiplexers, and bank arbitration logic including first arbiters including a first arbiter and second arbiters including a second arbiter, the first arbiter coupled to the second arbiter, the second and third multiplexers, the second arbiter coupled to the first multiplexer.

Abstract: Software instructions are executed on a processor within a computer system to configure a steaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a specified width for two selected dimensions of the array. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. When either selected dimension in the stream of vectors exceeds a respective specified width, the streaming engine inserts null elements into each portion of a respective vector for the selected dimension that exceeds the specified width in the stream of vectors. Stream vectors that are completely null are formed by the streaming engine without accessing the system memory for respective data.

Abstract: A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.

Abstract: A caching system including a first sub-cache, and a second sub-cache coupled in parallel with the first sub-cache; wherein the second sub-cache includes line type bits configured to store an indication that a corresponding line of the second sub-cache is configured to store write-miss data.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to forward and invalidate inflight data in a store queue. An example apparatus includes a cache storage, a cache controller coupled to the cache storage and operable to receive a first memory operation, determine that the first memory operation corresponds to a read miss in the cache storage, determine a victim address in the cache storage to evict in response to the read miss, issue a read-invalidate command that specifies the victim address, compare the victim address to a set of addresses associated with a set of memory operations being processed by the cache controller, and in response to the victim address matching a first address of the set of addresses corresponding to a second memory operation of the set of memory operations, provide data associated with the second memory operation.

Abstract: Methods, apparatus, systems and articles of manufacture to facilitate an atomic operation and/or a histogram operation in cache pipeline are disclosed An example system includes a cache storage coupled to an arithmetic component; and a cache controller coupled to the cache storage, wherein the cache controller is operable to: receive a memory operation that specifies a set of data; retrieve the set of data from the cache storage; utilize the arithmetic component to determine a set of counts of respective values in the set of data; generate a vector representing the set of counts; and provide the vector.

Abstract: A concrete mixer vehicle includes a trainer cab that is coupled to a chassis and arranged laterally outwardly relative to a main cab. The trainer cab includes: (a) a seat mounted to a recessed mounting floor that is arranged rearward of a wheel well, (b) a support beam that includes an air vent and air flow path integrated into the support beam, or (c) a windshield wiper with a park location that is arranged between a trainer cab column and a superstructure support so that the windshield wiper is hidden from being viewed from within the main cab.

Abstract: A concrete mixer vehicle includes a controller that is configured to detect that an engine is in an idle condition and selectively shutdown the engine in response to detecting that one or more override conditions are met.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate read-modify-write support in a victim cache. An example apparatus includes a first storage coupled to a controller, a second storage coupled to the controller and parallel coupled to the first storage, and a storage queue coupled to the first storage, the second storage, and to the controller, the storage queue to obtain a memory operation from the controller indicating an address and a first set of data, obtain a second set of data associated with the address from at least one of the first storage and the second storage, merge the first set of data and the second set of data to produce a third set of data, and provide the third set of data for writing to at least one of the first storage and the second storage.

Abstract: A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to forward and invalidate inflight data in a store queue. An example apparatus includes a cache storage, a cache controller coupled to the cache storage and operable to receive a first memory operation, determine that the first memory operation corresponds to a read miss in the cache storage, determine a victim address in the cache storage to evict in response to the read miss, issue a read-invalidate command that specifies the victim address, compare the victim address to a set of addresses associated with a set of memory operations being processed by the cache controller, and in response to the victim address matching a first address of the set of addresses corresponding to a second memory operation of the set of memory operations, provide data associated with the second memory operation.

Abstract: A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values are sorted in an order indicated by the vector sort instruction, and storing the sorted vector in a storage location.

Abstract: A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.