Abstract: Techniques for caching data are provided that include receiving, by a caching system, a write memory command for a memory address, the write memory command associated with a first color tag, determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache, determining, by second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, storing first data associated with the first write memory command in a cache line of the second sub-cache, storing the first color tag in the second sub-cache, receiving a second write memory command for the cache line, the write memory command associated with a second color tag, merging the second color tag with the first color tag, storing the merged color tag, and evicting the cache line based on the merged color tag.

Abstract: An integrated circuit, comprising an instruction pipeline that includes instruction fetch phase circuitry, instruction decode phase circuitry, and instruction execution circuitry. The instruction execution circuitry includes transformation circuitry for receiving an interleaved dual vector operand as an input and for outputting a first natural order vector including a first set of data values from the interleaved dual vector operand and a second natural order vector including a second set of data values from the interleaved dual vector operand.

Abstract: Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.

Abstract: Disclosed embodiments relate to methods of using a processor to load and duplicate scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.

Abstract: Provided are food products that have structures, textures, and other properties comparable to those of animal meat, and that may therefore serve as substitutes for animal meat. Also provided are processes for production of such ground meat-like food products.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding. An example apparatus includes a first storage, a second storage, a store queue coupled to the first storage and the second storage, the store queue operable to receive a first memory operation specifying a first set of data, process the first memory operation for storing the first set of data in at least one of the first storage and the second storage, receive a second memory operation, and prior to storing the first set of data in the at least one of the first storage and the second storage, feedback the first set of data for use in the second memory operation.

Abstract: Methods of stabilizing acidic cannabinoids by intercalating the acidic cannabinoids into layered double hydroxides (LFHs) are provided. Also provided are compositions comprising the LDH-intercalated acidic cannabinoids, physiologically compatible formulations comprising the compositions and methods of using the formulations to treat a variety of diseases and conditions in subjects.

Abstract: Disclosed herein are systems, methods, and devices for sensing touch at a surface. Sensing touch can be achieved while decreasing the number of sensors at a surface as well as data and computation complexity, but maintaining accuracy. Such sensing touch can be achieved via applying excitation and detecting emission waveforms at a surface that are associated with touch at a surface.

Abstract: A digital signal processor having a CPU with a program counter register and, optionally, an event context stack pointer register for saving and restoring the event handler context when higher priority event preempts a lower priority event handler. The CPU is configured to use a minimized set of addressing modes that includes using the event context stack pointer register and program counter register to compute an address for storing data in memory. The CPU may also eliminate post-decrement, pre-increment and post-decrement addressing and rely only on post-increment addressing.

Abstract: Described herein is a computer implemented method. The method includes detecting user input activating a text effect selection control. In response to the user input the method further includes automatically determining a selected design element, the selected design element being a text element displayed on a page; applying a stroke to the selected design element; setting a fill of the selected design element to be transparent; and generating and displaying a shadow for the selected design element.

Abstract: A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, generating a control input vector for vector permutation logic comprised in the processor based on values in lanes of the vector and a sort order for the vector indicated by the vector sort instruction and storing the control input vector in a storage location.

Abstract: Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.

Abstract: A ring toss game apparatus including a ring; a line suspending the ring from a support for manually induced movement of the ring; a housing for mounted disposition a predetermined length away from the ring; a hook mounted to the housing for ring capture through the hook opening; means for providing a control signal responsive to the hook operatively capturing the ring; and means for engaging the ring and moving the ring off the hook wherein games may be played by urging the ring toward the hook with the objective of each iteration being operative engagement of the ring with the hook, resulting in operation of the means for engaging the ring and moving the ring off the hook, thereby allowing another attempt at hook engagement without the player having to approach the hook and manually remove the ring.

Abstract: Devices, systems, and methods of evaluating risk associated with a condition of the vessel and issuing an automatic recommendation based on co-registered physiological measurements are disclosed. The includes steps of obtaining image data for the vessel of the patient, obtaining physiological measurements for the vessel of the patient, co-registering the obtained physiological measurements with the obtained image data such that the physiological measurements are associated with corresponding portions of the vessel of the patient, analyzing the co-registered physiology measurements to identify a region of interest, and outputting, to a user interface, a suggested diagnostic procedure for the region of interest based on the analysis of the co-registered physiology measurements.

Abstract: A method of clearing of registers and logic designs with AND and OR logics to propagate the zero values provided to write enable signal buses upon the execution of clear instruction of more than one registers, allowing more than one architecturally visible registers to be cleared with one signal instruction regardless of the values of data buses.

Abstract: A load control system may be provided including control devices and a system controller. The system controller may be configured to broadcast a service set identifier (SSID) and provide a wireless network connection to a network device. The system controller may provide a web page to the network device, wherein the web page may include an indication of target system controllers. The target system controllers may be used for configuring (e.g., associating) the control devices. The system controller may receive an indication of a target system controller selected to associate the control devices. The system controller may determine an address and port number of the target system controller identified by the network device. The system controller may provide, to the network device, the web page from the target system controller while the network device is connected to the system controller via the wireless network connection.

Abstract: Various configurations of processors are provided. In a configuration, the processor comprises first and second multiplication unit. Each of these multiplication units includes carry-save adder circuitry with a respective outputs, partial product alignment multiplexing logic coupled to the outputs of the associated carry-save adder circuitry. The processor further comprises communication paths coupled between the outputs of the carry-save adder circuitry of the first multiplication unit and the partial product alignment multiplexing logic of the second multiplication unit. In other configurations, each of the first and second multiplication units may include one or more instances of masking logic, one or more instances of a multiplier array coupled to the associated instance(s) of masking logic, and one or more instances of a multiplexer set coupled to the associated instance(s) of multiplier array(s).

Abstract: A method of evaluating a vessel of a patient is provided. The method includes outputting, to a display device, a screen display including: a visualization based on pressure measurements obtained from a first instrument and a second instrument positioned within the vessel of the patient while the second instrument is moved longitudinally through the vessel and the first instrument remains stationary within the vessel; and a visual representation of a vessel; receiving a user input to modify the visualization to simulate a therapeutic procedure; and updating the screen display, in response to the user input, including modifying the visualization based on the user input. A system for evaluating a vessel of a patient is also provided. The system includes first and second instruments sized and shaped for introduction into the vessel of the patient; and a processing system communicatively coupled to the first and second instruments and a display device.

Abstract: A device, such as Network Microphone Device or a playback device, detecting an event associated with the device or a system comprising the device. In response, an input detection window is opened for a given time period. During the given time period the device is arranged to receive an input sound data stream representing sound detected by a microphone. The input sound data stream is analyzed for a plurality of keywords and/or a wake-word for a Voice Assistant Service (VAS) and, based on the analysis, it is determined that the input sound data stream includes voice input data comprising a keyword or a wake-word for a VAS. In response, the device takes appropriate action such as causing the media playback system to perform a command corresponding to the keyword or sending at least part of the input sound data stream to the VAS.

Abstract: A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing write-memory commands that are not cached in the first sub-cache, the second sub-cache including privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a level of privilege, and wherein the second sub-cache is further configured to receive a first write memory command for a memory address associated with a first level of privilege, store, in the second sub-cache, first data associated with the first write memory command and the level of privilege associated with the cache line, receive a second write memory command for the cache line, the second write memory command associated with a second level of privilege, merge the first level of privilege with the second level of privilege, and output the merged privilege level with the cache line.