Abstract: Ceramic nanocomposite and methods for manufacturing thereof. One method comprising: receiving a fired green ceramic body comprising ceramic matrix; introducing to the fired green ceramic body submicron particles; and introducing at least one type of location-controlling dopant at an amount that is sufficient to cover the majority of the ceramic matrix grain boundaries, as well as the majority of the interfaces between the submicron particles and the ceramic matrix grains but less than an amount that would result in a concentration that exceeds the bulk solubility limit of the location-controlling dopant ions in the ceramic matrix, at the ceramic nanocomposite sintering temperature.

Abstract: The present invention provides a method and apparatus for handling critical blocking of store-to-load forwarding. One embodiment of the method includes recording a load that matches an address of a store in a store queue before the store has valid data. The load is blocked because the store does not have valid data. The method also includes replaying the load in response to the store receiving valid data so that the valid data is forwarded from the store queue to the load.

Abstract: The present invention provides a method and apparatus for saving and restoring soft repair information. One embodiment of the method includes storing soft repair information for one or more cache arrays implemented in a processor core in a memory element outside of the processor core in response to determining that a voltage supply to the processor core is to be disconnected.

Abstract: The present invention provides a method and apparatus for use with a hierarchical cache system. The method may include concurrently flushing one or more first caches and a second cache of a multi-level cache. Each first cache is smaller and at a lower level in the multi-level cache than the second level cache.

Abstract: A method of operating a processor includes reclaiming a physical register renamed as a microcode architectural register used by a microcode routine. The physical register is reclaimed according to an indicator corresponding to the microcode architectural register and indicating that a pointer to the physical register and corresponding to the microcode architectural register is an active pointer.

Abstract: We have discovered that p63 inhibition results in increased cellular proliferation. We have also performed a screen for agents capable of increasing cellular proliferation, (e.g., of stem cells such as skin-derived precursors (SKPs)). The invention therefore invention provides compositions, methods, and kits for increasing proliferation of cells, using compounds that decrease p63 expression or activity or using the compounds described herein. The invention also features methods of using these compounds for increasing hair growth, improving skin health, or promoting skin repair in a subject.

Abstract: A microsequencer is disclosed that controls the order in which microcode instructions are fetched from a microcode ROM. Each microcode instruction includes an execution command for execution by one or more execution units. Each microcode instruction also includes a microsequencer command to indicate the location of another microcode instruction at the microcode ROM. The microcode instruction can also include a delay field, indicating a selectable time when the associated microcode instruction is to be decoded. The delay field thereby provides more flexible control of the sequencing of microcode instructions.

Abstract: An efficient method and system for wireless database management that allows database administrators to monitor and manage a plurality of databases from a remote location is disclosed. Included in this description are steps for reducing the amount of data transmitted and received by narrow bandwidth wireless communications, storing the results of requests made by the same user repeatedly for quicker access time, and enabling a single user to access multiple databases within the wireless database management system simultaneously.

Abstract: A plow shovel configured to create a path in snow by pushing the snow along a surface without lifting the snow. The plow shovel has a handle attached to a scoop having a first side and a second side. The scoop has a multi-sided plow component configured to part snow and makes a path without lifting the shovel as the plow shovel is pushed forward. A method of clearing a path in snow using the plow shovel described is also provided.

Abstract: Provided herein are implantable biomedical devices and methods of administering implantable biomedical devices, making implantable biomedical devices, and using implantable biomedical devices to actuate a target tissue or sense a parameter associated with the target tissue in a biological environment.

Abstract: The present invention provides for compositions and methods for preparing aqueous insoluble, ductile, flexible silk fibroin films. The silk films comprise silk fibroin and about 10% to about 50% (w/w) glycerol, and are prepared by entirely aqueous processes. The ductile silk film may be further treated by extracting the glycerol from and re-drying the silk film. Active agents may be embedded in or deposited on the glycerol modified silk film for a variety of medical applications. The films may be into 3-dimentional structures, or placed on support surfaces as labels or coatings. The glycerol modified silk films of the present invention are useful in variety of applications such as tissue engineering, medical devices or implants, drug delivery, and edible pharmaceutical or food labels.

Abstract: In an embodiment, a guest interrupt control unit in a hardware processor may be configured to detect that an interrupt has been recorded in a memory location corresponding to a virtual processor, wherein the interrupt is targeted at the virtual processor. In response to the virtual processor being active on the hardware processor, the guest interrupt control unit is configured to provide the interrupt to the guest that includes the virtual processor. In an embodiment, a processor is configured to execute instructions from a guest, wherein the processor is configured to detect an instruction that accesses interrupt controller state data associated with a virtual processor in the guest, and wherein the processor is configured to access a memory location that stores interrupt controller state data corresponding to the virtual processor in response to the instruction.

Abstract: In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an operation targeted to a memory location in a system memory to record the interrupt for a virtual processor within the guest, wherein the interrupt is to be delivered to the targeted virtual processor. In an embodiment, a virtual machine manager may be configured to detect that an interrupt has been recorded by the device interrupt manager for a virtual processor that is not currently executing. The virtual machine manager may be configured to schedule the virtual processor for execution on a hardware processor, or may prioritize the virtual processor for scheduling, in response to the interrupt.

Abstract: An address containing data to be accessed is determined in response to executing an instruction received at a processor core of a microprocessor. During a scratch-pad mode of operation, it is determined whether a set of cache lines of a data cache is accessible based upon the memory location from which the instruction was retrieved. The address space of the data cache during scratch-pad mode can be isolated from other address spaces.

Abstract: A Distributed Energy Resources Manager may serve to connect electrical assets in an electricity distribution grid with other information-processing systems including, but not limited to, existing utility grid management systems to manage flows of information between electrical assets and interacting software assets and, thereby, manage performance of at least the electrical assets.

Abstract: A method and apparatus for branch determination. The method includes a first command issuing within a computer processor, wherein execution of the first command by the computer processor includes evaluating one or more conditions to set one or more flags. The method further includes a second command issuing, subsequent to the first command issuing, within the computer processor, wherein execution of the second command by the computer processor includes causing the computer processor to wait until the one or more flags are set. Subsequent to the first and second commands issuing, the method includes a third command issuing within the computer processor, wherein execution of the third command by the computer processor includes performing a jump operation based on a value of at least one of the one or more flags set by the first command.

Abstract: A microsequencer is disclosed that controls the order in which microcode instructions are fetched from a microcode ROM. Each microcode instruction includes an execution command for execution by one or more execution units. Each microcode instruction also includes a microsequencer command to indicate the location of another microcode instruction at the microcode ROM. The microcode instruction can also include a delay field, indicating a selectable time when the associated microcode instruction is to be decoded. The delay field thereby provides more flexible control of the sequencing of microcode instructions.

Abstract: A system and method for efficient architectural register liveness analysis and register usage reduction. A compiler within a computing system maintains a master liveness vector for each instruction in a program code and a path liveness vector for each path within a predetermined control flow graph (CFG). Predetermined required paths from an earlier compiler stage are used to find force paths, which are used to reduce the number of times a control block (CB) is processed. Upon completion of the liveness analysis, the compiler finds an instruction within the program code where a chosen register previously dead is now live. The compiler identifies allocation code paths from this instruction, wherein each path terminates at an instruction wherein the chosen register is dead for the first time in the allocation code path. The compiler subsequently replaces the chosen register with a determined dead register.

Abstract: A system, a method and an apparatus are provided for the wireless monitoring and management of computer systems, networks, software systems or databases on a portable and/or handheld device which may monitor, update, and fix the system from any location and at any time. More specifically, the system, the method and the apparatus provide for the wireless monitoring and management of such systems by formatting information on a handheld screen of a wireless device, automatically wrapping portions of information for browsing on wireless devices, displaying information in a graph or other format on a wireless device, and/or auto-scaling of graphs on a wireless device.