Abstract: A silk fiber based matrix composition comprising spider silk that can be biodegradable, from the spider species Nephila clavipes (or from genetically engineered bacteria making Nephila clavipes silk), and in the form of a mesh or film.

Abstract: A method includes executing microcode in a processing unit of a processor to implement a machine instruction, wherein the microcode is to manipulate the processing unit to access a peripheral device on a public communication bus at a private address not visible to other devices on the public communication bus and not specified in the machine instruction. A processor includes a public communication bus, a peripheral device coupled to the public communication bus, and a processing unit. The processing unit is to execute microcode to implement a machine instruction. The microcode is to manipulate the processing unit to access a peripheral device on a public communication bus at a private address not visible to other devices on the public communication bus and not specified in the machine instruction.

Abstract: A method includes executing microcode in a processing unit of a processor to implement a machine instruction, wherein the microcode is to manipulate the processing unit to access a peripheral device on a public communication bus at a private address not visible to other devices on the public communication bus and not specified in the machine instruction. A processor includes a public communication bus, a peripheral device coupled to the public communication bus, and a processing unit. The processing unit is to execute microcode to implement a machine instruction. The microcode is to manipulate the processing unit to access a peripheral device on a public communication bus at a private address not visible to other devices on the public communication bus and not specified in the machine instruction.

Abstract: A microfluidic device includes, in one embodiment, a first silk film coupled to a second silk film with at least one microchannel therebetween.

Abstract: Ceramic nanocomposites and methods for manufacturing the ceramic nanocomposites are disclosed. One method includes introducing to a fired green ceramic body having a ceramic matrix submicron particles having coefficient of thermal expansion lower than the coefficient of thermal expansion of the ceramic matrix and at least one type of location-controlling dopant at an amount that is sufficient to cover the majority of the ceramic matrix grain boundaries. One ceramic nanocomposite includes a ceramic matrix with submicron particles dispersed in the ceramic matrix, the submicron particles having a coefficient of thermal expansion lower than the coefficient of thermal expansion of the ceramic matrix and at least one dopant that covers the majority of the ceramic matrix grain boundaries, at a concentration that does not exceed the bulk solubility limit of the dopant in the ceramic matrix at the ceramic nanocomposite sintering temperature.

Abstract: The present invention provides silk photonic crystals that can be used to enhance light-induced effects. Also disclosed are biocompatible, functionalized, all-protein inverse opals and related methods.

Abstract: The present invention provides a method and apparatus for saving and restoring soft repair information. One embodiment of the method includes storing soft repair information for one or more cache arrays implemented in a processor core in a memory element outside of the processor core in response to determining that a voltage supply to the processor core is to be disconnected.

Abstract: The present invention relates to compositions and methods for diagnosing and treating diseases, disorders or conditions associated with dysregulated expression of GPC3. The invention provides novel antibodies that specifically bind to glypican-3 (GPC3). The invention also relates to a fully human chimeric antigen receptor (CAR) wherein the CAR is able to target GPC3.

Abstract: A processor includes a cache memory, a first core including an instruction execution unit, and a memory bus coupling the cache memory to the first core. The memory bus is operable to receive a first portion of a cache line of data for the cache memory, the first core is operable to identify a plurality of data requests targeting the cache line and the first portion and select one of the identified plurality of data requests for execution, and the memory bus is operable to forward the first portion to the instruction execution unit and to the cache memory in parallel.

Abstract: The present application describes embodiments of a method and apparatus including a page cross misalign buffer. Some embodiments of the apparatus include a store queue for a plurality of entries configured to store information associated with store instructions. A respective entry in the store queue can store a first portion of information associated with a page crossing store instruction. Some embodiments of the apparatus also include one or more buffers configured to store a second portion of information associated with the page crossing store instruction.

Abstract: The present invention provides a method and apparatus for allocating store queue entries to store instructions for early store-to-load forwarding. Some embodiments of the method include allocating an entry in a store queue to a store instruction in response to the store instruction being dispatched and prior to receiving a translation of a virtual address to a physical address associated with the store instruction. The entry includes storage for data to be written to the physical address by the store instruction.

Abstract: The present invention provides a method and apparatus for generating eligible store maps for store-to-load forwarding. Some embodiments of the method include generating information associated with a load instruction in a load queue. The information indicates whether one or more store instructions in a store queue is older than the load instruction and whether the store instruction(s) overlap with any younger store instructions in the store queue that are older than the load instruction. Some embodiments of the method also include determining whether to forward data associated with a store instruction to the load instruction based on the information. Some embodiments of the apparatus include a load-store unit that implements embodiments of the method.

Abstract: We have discovered that p63 inhibition results in increased cellular proliferation. We have also performed a screen for agents capable of increasing cellular proliferation, (e.g., of stem cells such as skin-derived precursors (SKPs)). The invention therefore invention provides compositions, methods, and kits for increasing proliferation of cells, using compounds that decrease p63 expression or activity or using the compounds described herein. The invention also features methods of using these compounds for increasing hair growth, improving skin health, or promoting skin repair in a subject.

Abstract: Ceramic nanocomposite and methods for manufacturing thereof. One method comprising: receiving a fired green ceramic body comprising ceramic matrix; introducing to the fired green ceramic body submicron particles; and introducing at least one type of location-controlling dopant at an amount that is sufficient to cover the majority of the ceramic matrix grain boundaries, as well as the majority of the interfaces between the submicron particles and the ceramic matrix grains but less than an amount that would result in a concentration that exceeds the bulk solubility limit of the location-controlling dopant ions in the ceramic matrix, at the ceramic nanocomposite sintering temperature.

Abstract: A method and apparatus for branch determination is disclosed. The method includes a first command issuing within a computer processor. Execution of the first command by the computer processor includes evaluating one or more conditions to set one or more flags. Subsequent to the first command issuing, a second command is issued and executed. Execution of the second command includes causing the computer processor to wait until the one or more flags are set. Subsequent to the first and second commands issuing, a third command is issued and executed. Execution of the third command includes performing a jump operation based on a value of at least one of the one or more flags set by the first command.

Abstract: A processing core in a multi-processing core system is configured to execute a sequence of instructions as a single atomic memory transaction. The processing core validates that the sequence meets a set of one or more atomicity criteria, including that no instruction in the sequence instructs the processing core to access shared memory. After validating the sequence, the processing core executes the sequence as a single atomic memory transaction, such as by locking a source cache line that stores shared memory data, executing the validated sequence of instructions, storing a result of the sequence into the source cache line, and unlocking the source cache line.

Abstract: A random number generator may include an input configured to receive a plurality of entropy bits generated by an entropy source of a random number generator, wherein the random number generator is configured to generate a plurality of random numbers; and an entropy health monitor coupled with the input, wherein the entropy health monitor is configured to perform a corrective action based on the plurality of entropy bits.

Abstract: A sensor input into a first near field communication (NFC) device, such as an accelerometer input resulting from a rapid motion of the first NFC device to the right, is associated with a function of a second NFC device, such as a zoom function. The first NFC device is brought into proximity to a second NFC device and an NFC operation is launched. If the sensor input into the first NFC device is detected during a time window including the NFC launch time, the first NFC device communicates instructions to the second NFC device to execute the function, and the function is executed by the second NFC device.

Abstract: A system includes a processor including at least a first core and a local interrupt controller associated with the first core. The first core is operable to store its architectural state prior to entering a first core sleep state, and the processor is operable to receive and implement a request for entering a system sleep state in which the first core is in the first core sleep state and the local interrupt controller is powered down and exit the system sleep state by restoring the local interrupt controller and restoring the saved architectural state of the first core.

Abstract: A processor, a method and a computer-readable storage medium for tracking a return address are provided. The processor comprises a hardware register and logic configured to receive a call instruction. The logic is further configured to, based on the call instruction, encrypt a return address, store the encrypted return address onto a first address in a stack and store the first address on the hardware register.