Patents by Inventor David A. Pritchard

David A. Pritchard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11108882
    Abstract: Embodiments of the present invention provide a system for assessing role defining parameters associated with access to resources in a network. The system is configured for extracting information associated with one or more resources, one or more users, and one or more authorizations, determining one or more metrics associated with one or more roles within an entity based on the extracted information, calculating a role defining parameter that defines a condition of the one or more roles based on the one or more metrics associated with the one or more roles, wherein the role defining parameter is associated with access to the one or more resources, determining if the parameter is below a predefined threshold, and performing one or more actions.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: August 31, 2021
    Assignee: BANK OF AMERICA CORPORATION
    Inventors: Rajesh Gopinathapai, Jennifer Greenwald, David Pritchard
  • Patent number: 11094791
    Abstract: One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: August 17, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Heng Yang, David Pritchard, Kai Sun, Hongru Ren, Neha Nayyar, Manjunatha Prabhu, Elizabeth Strehlow, Salvatore Cimino
  • Publication number: 20210242316
    Abstract: One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.
    Type: Application
    Filed: January 30, 2020
    Publication date: August 5, 2021
    Inventors: Heng Yang, David Pritchard, Kai Sun, Hongru Ren, Neha Nayyar, Manjunatha Prabhu, Elizabeth Strehlow, Salvatore Cimino
  • Publication number: 20210242094
    Abstract: One illustrative vertical transistor device disclosed herein includes a channel region comprising at least one layer of a two-dimensional (2D) material, a bottom source/drain region, a top source/drain region and a gate structure positioned all around at least the at least one layer of a two-dimensional (2D) material.
    Type: Application
    Filed: January 30, 2020
    Publication date: August 5, 2021
    Inventors: Heng Yang, David Pritchard, Kai Sun, Hongru Ren, Neha Nayyar, Manjunatha Prabhu, Elizabeth Strehlow, Salvatore Cimino
  • Publication number: 20210176331
    Abstract: Embodiments of the present invention provide a system for assessing role defining parameters associated with access to resources in a network. The system is configured for extracting information associated with one or more resources, one or more users, and one or more authorizations, determining one or more metrics associated with one or more roles within an entity based on the extracted information, calculating a role defining parameter that defines a condition of the one or more roles based on the one or more metrics associated with the one or more roles, wherein the role defining parameter is associated with access to the one or more resources, determining if the parameter is below a predefined threshold, and performing one or more actions.
    Type: Application
    Filed: December 9, 2019
    Publication date: June 10, 2021
    Applicant: BANK OF AMERICA CORPORATION
    Inventors: Rajesh Gopinathapai, Jennifer Greenwald, David Pritchard
  • Publication number: 20210057558
    Abstract: A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Inventors: David Pritchard, Heng Yang, Hongru Ren, Neha Nayyar, Manjunatha Prabhu, Elizabeth Strehlow, Salvatore Cimino
  • Publication number: 20210056442
    Abstract: Aspects of the disclosure relate to identifying entitlement rules based on a frequent pattern tree. A computing platform may retrieve entitlement data associated with a relational database, where the entitlement data is indicative of user entitlements to computing resources in an enterprise network. Then, the computing platform may generate, for the entitlement data, a frequent pattern tree. Then, the computing platform may compare a pair of branches and may detect a pattern associated with a pair of entitlements. Then, the computing platform may determine, based on the frequent pattern tree, a frequency of occurrence of the pattern. Then, the computing platform may identify, based on the frequency of occurrence, a rule associated with the pattern. Subsequently, the computing platform may trigger, via the computing device and based on the rule, an action related to one or more of the entitlements of the pair of entitlements.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Inventors: David Pritchard, Rajesh Gopinathapai, Jennifer Lynn Greenwald
  • Publication number: 20200410410
    Abstract: A computer-implemented method for automated forecasting of cash flow includes: monitoring, while a plurality of first transactions are being processed in a payment network, payable transaction data associated with the plurality of first transactions, the plurality of first transactions initiated with at least one account issued to a merchant; monitoring, while a plurality of second transactions are being processed in a payment network, receivable transaction data associated with the plurality of second transactions, the plurality of second transactions between the merchant and a plurality of users; determining, based on the payable transaction data and the receivable transaction data, a plurality of seasonal variables; and generating a cash flow forecast associated with the merchant, the cash flow forecast generated based on the plurality of seasonal variables. A system and computer program product for automated forecasting of cash flow are also disclosed.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Anup Tripathi, Robert David Pritchard, Jr., Yinle Zhou, Suman Mukherjee
  • Publication number: 20200299012
    Abstract: A unit for mixing and dispensing an aerosol precursor composition, and containers to be dispensed therefrom. The unit includes a plurality of bulk material filling stations, the plurality of bulk material filling stations have at least one first filling station with aerosol former and at least one second filling station with a flavor material for creating the aerosol precursor. The unit also includes a bulk consumable pack staging a plurality of containers configured to receive the aerosol precursor, and a robot configured to retrieve a container from the bulk consumable pack and move the container through at least two dimensions to stop at at least two of the plurality of bulk material filling stations.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Applicant: RAI Strategic Holdings, Inc.
    Inventors: Andries Don Sebastian, Charles Jacob Novak, III, Alvaro Gonzalez-Parra, Eugenia Theophilus, Marielle Anitra Keyna des Etages, Joseph Dominique, Wesley Steven Jones, Bradley Phillips, Mark Dockrill, Simon A. English, Simon Philip Adam Higgins, Thomas Crugnale, Jeffrey Hughes, Robert Neil, David Pritchard
  • Patent number: 10759554
    Abstract: A unit for mixing and dispensing an aerosol precursor composition, and containers to be dispensed therefrom. The unit includes a plurality of bulk material filling stations, the plurality of bulk material filling stations have at least one first filling station with aerosol former and at least one second filling station with a flavor material for creating the aerosol precursor. The unit also includes a bulk consumable pack staging a plurality of containers configured to receive the aerosol precursor, and a robot configured to retrieve a container from the bulk consumable pack and move the container through at least two dimensions to stop at least two of the plurality of bulk material filling stations.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: September 1, 2020
    Assignee: RAI STRATEGIC HOLDINGS, INC.
    Inventors: Andries Don Sebastian, Charles Jacob Novak, III, Alvaro Gonzalez-Parra, Eugenia Theophilus, Marielle Anitra Keyna des Etages, Joseph Dominique, Wesley Steven Jones, Bradley Phillips, Mark Dockrill, Simon A. English, Simon Philip Adam Higgins, Thomas Crugnale, Jeffrey Hughes, Robert Neil, David Pritchard
  • Patent number: 10727108
    Abstract: The present disclosure relates to an isolation region between semiconductor devices and methods of fabrication. Embodiments include device having a silicon-on-insulator (SOI) substrate; a dummy gate between two metal gates formed over the SOI substrate, the dummy gate providing a physical diffusion break between the two metal gates; raised source/drain (S/D) regions formed on sides of the metal gates; and interlayer dielectric formed over the dummy gate, raised S/D regions and metal gates and in openings on sides of the dummy gate.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: July 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: David Pritchard, Heng Yang, Hongru Ren
  • Patent number: 10651136
    Abstract: When forming semiconductor devices, plasma-induced damage may be prevented or restricted by providing a conductive path between critical areas and the substrate of the semiconductor device. According to the present disclosure, a negative effect of any such protective structures on the performance of the semiconductor device may be significantly reduced by permanently interrupting the corresponding electrical connection at any appropriate point in time of the manufacturing sequence. Furthermore, respective fuse structures acting as current-sensitive areas may also be implemented in test structures in order to evaluate plasma-induced currents, thereby providing a possibility for a more efficient design of respective protective structures and/or for contributing to superior process control of critical plasma treatments.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: David Pritchard, Lixia Lei, Francisco Ledesma Rabadan
  • Publication number: 20200127013
    Abstract: The present disclosure relates to an isolation region between semiconductor devices and methods of fabrication. Embodiments include device having a silicon-on-insulator (SOI) substrate; a dummy gate between two metal gates formed over the SOI substrate, the dummy gate providing a physical diffusion break between the two metal gates; raised source/drain (S/D) regions formed on sides of the metal gates; and interlayer dielectric formed over the dummy gate, raised S/D regions and metal gates and in openings on sides of the dummy gate.
    Type: Application
    Filed: October 23, 2018
    Publication date: April 23, 2020
    Inventors: David PRITCHARD, Heng YANG, Hongru REN
  • Patent number: 10529704
    Abstract: One illustrative embodiment disclosed herein relates to a semiconductor device that includes, among other things, a semiconductor substrate including a base semiconductor layer, an active semiconductor layer, and a buried insulating layer positioned between the base semiconductor layer and the active semiconductor layer. The device further includes a set of functional gate structures including at least one functional gate structure formed above the active semiconductor layer, a first source/drain region positioned in the active semiconductor layer adjacent a first functional gate structure in the set, a first auxiliary gate structure positioned adjacent the first source/drain region, and a discharge device coupled to the base semiconductor layer and the first auxiliary gate structure.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: January 7, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Salvatore Cimino, David Pritchard, Lixia Lei, Heng Yang, Manjunatha Prabhu
  • Patent number: 10347543
    Abstract: A method of forming contacts includes forming a plurality of transistor devices separated by shallow trench insulator regions, the transistor devices each comprising a semiconductor substrate, a buried insulator layer on the semiconductor bulk substrate, a semiconductor layer on the buried insulator layer, a high-k metal gate stack on the semiconductor layer and a gate electrode above the high-k metal gate stack, raised source/drain regions on the semiconductor layer, and a silicide contact layer above the raised source/drain regions and the gate electrode, providing an interlayer dielectric stack on the silicide contact layer and planarizing the interlayer dielectric stack, patterning a plurality of contacts through the interlayer dielectric stack onto the raised source/drain regions, and, for at least some of the contacts, patterning laterally extended contact regions above the contacts, the laterally extended contact regions extending over shallow trench insulator regions neighboring the corresponding rais
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Rick Carter, Vikrant Chauhan, George Jonathan Kluth, Anurag Mittal, David Pritchard, Mahbub Rashed
  • Publication number: 20190148245
    Abstract: A method of forming contacts includes forming a plurality of transistor devices separated by shallow trench insulator regions, the transistor devices each comprising a semiconductor substrate, a buried insulator layer on the semiconductor bulk substrate, a semiconductor layer on the buried insulator layer, a high-k metal gate stack on the semiconductor layer and a gate electrode above the high-k metal gate stack, raised source/drain regions on the semiconductor layer, and a silicide contact layer above the raised source/drain regions and the gate electrode, providing an interlayer dielectric stack on the silicide contact layer and planarizing the interlayer dielectric stack, patterning a plurality of contacts through the interlayer dielectric stack onto the raised source/drain regions, and, for at least some of the contacts, patterning laterally extended contact regions above the contacts, the laterally extended contact regions extending over shallow trench insulator regions neighboring the corresponding rais
    Type: Application
    Filed: November 13, 2017
    Publication date: May 16, 2019
    Inventors: Peter Baars, Rick Carter, Vikrant Chauhan, George Jonathan Kluth, Anurag Mittal, David Pritchard, Mahbub Rashed
  • Publication number: 20190074257
    Abstract: When forming semiconductor devices, plasma-induced damage may be prevented or restricted by providing a conductive path between critical areas and the substrate of the semiconductor device. According to the present disclosure, a negative effect of any such protective structures on the performance of the semiconductor device may be significantly reduced by permanently interrupting the corresponding electrical connection at any appropriate point in time of the manufacturing sequence. Furthermore, respective fuse structures acting as current-sensitive areas may also be implemented in test structures in order to evaluate plasma-induced currents, thereby providing a possibility for a more efficient design of respective protective structures and/or for contributing to superior process control of critical plasma treatments.
    Type: Application
    Filed: September 5, 2017
    Publication date: March 7, 2019
    Inventors: David Pritchard, Lixia Lei, Francisco Ledesma Rabadan
  • Patent number: 10186524
    Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: January 22, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: David Pritchard, Lixia Lei, Deniz E. Civay, Scott D. Luning, Neha Nayyar
  • Patent number: 10181522
    Abstract: Structures for a field-effect transistor and fabrication methods for forming a structure for a field-effect transistor. The structure may include a gate electrode, a source/drain region formed adjacent to a vertical sidewall of the gate electrode, and a conductive link that couples the vertical sidewall of the gate electrode with the source/drain region.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: January 15, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tuhin Guha Neogi, Scott D. Luning, David Pritchard, Kasun Anupama Punchihewa
  • Publication number: 20180240885
    Abstract: Structures for a field-effect transistor and fabrication methods for forming a structure for a field-effect transistor. The structure may include a gate electrode, a source/drain region formed adjacent to a vertical sidewall of the gate electrode, and a conductive link that couples the vertical sidewall of the gate electrode with the source/drain region.
    Type: Application
    Filed: February 21, 2017
    Publication date: August 23, 2018
    Inventors: Tuhin Guha Neogi, Scott D. Luning, David Pritchard, Kasun Anupama Punchihewa