Abstract: A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.

Abstract: A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the first structures, in a second portion. The first and second structures are defined by lithography processes using photomasks. At least one of the photomasks includes both openings in a first region for supporting the definition of the first structures and openings in a second region for supporting the definition of the second structures.

Abstract: A windshield wiper assembly is provided having a unitary wiper arm and post, and a mechanical linkage for receiving the post and moving the arm. The post has a breakaway feature for breaking the post in response to impact. The wiper includes a head partially containing a center post and a button biased with a spring and connected to the center post for releasing the post from the linkage. The post and linkage include a captive ball and mating groove that are mutually engageable for securing the post to the linkage. Alternately, the post has a quick-connect end having a groove and the linkage has a receiving portion with a retractable collar and captive ball bearings. A vehicle is also provided including a windshield, a windshield wiper having a post, a wiper motor, and a mechanical linkage having an opening for receiving the post and powering the wiper.

Abstract: Semiconductor device with a first structure comprising a plurality of at least in part parallel linear structures, a second structure comprising a plurality of pad structures, forming at least in part one of the group of linear structure, curved structure, piecewise linear structure and piecewise curved structure which is positioned at an angle to the first structure, and the plurality of pad structures are intersecting at least one of the linear structures in the first structure. An electronic device with at least one semiconductor device, methods for manufacturing a semiconductor device and a mask system are also covered.

Abstract: A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.

Abstract: A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.

Abstract: The invention generally provides compositions and methods that promote wound healing. Such compositions comprise isolated L. sericata polypeptides having serine protease activity. Desirably, the serine protease degrades fibronectin. The invention further provides biologically active fragments of fibronectin that promote wound healing that are the degradation products of incubation with ES.

Abstract: A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.

Abstract: A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.

Abstract: A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.

Abstract: A mobile surveillance and/or security unit. The unit includes a trailer, a tower mounted to the trailer, a plurality of apparatus positioned on the tower, and at least one power source configured to provide power to the plurality of apparatus. In addition, at least one of the plurality of apparatus is a communication apparatus.

Abstract: A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.

Abstract: Methods and apparatus for monitoring grid-based computing resources are disclosed. Example embodiments provide for the determination and display of a variety of metrics. Data related to processor utilization by a plurality of applications is accumulated, aggregated, and normalized. At least one metric related to the use of the grid by the plurality of applications is assayed or otherwise determined from the aggregated, normalized data. An archive database for archival storage of at least some of the data can also be provided. In some embodiments, a Web server displays metrics via a Web page. In addition, provision can be made to verify the service level agreement (SLA) compliance of the various resources on the grid.

Abstract: The present invention is directed to a method of fabricating a local interconnect. A disclosed method involves forming two separate cavities in the ILD above two electrical contacts of a transistor. A first cavity extend down to an underlying etch stop layer. The first cavity is then filled with a protective layer. The second cavity is then formed adjacent to the first cavity and extends down to expose the underlying etch stop layer. The protective layer is removed to form an expanded cavity including the first and second cavities which expose the underlying etch stop layer in the expanded cavity. The etch stop material in the expanded cavity is also removed to expose an underlying gate contact and expose one of a source or drain contact. The gate contact is then electrically connected with one of the exposed source or drain contacts to form a local interconnect.

Abstract: A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.

Abstract: A method for maintaining a human hookworm strain is provided by infecting a non-human primate with a non-adapted or non-passaged human hookworm and maintaining the non-human primate. Methods of obtaining human hookworm materials and compositions, such as for use as a vaccine, are also provided, along with a model for maintaining and investigating human hookworm.

Abstract: An isolated protein, for use in treatment of wounds, is characterized in that it is secreted by the organism Lucilia sericata and it exhibits proteolytic activity against FITC-casein at a pH of 8.0 to 8.5. The protein exhibits proteolytic activity against Tosyl-Gly-Pro-Arg-AMC but not against Suc-Ala-Ala-Phe-AMC, and its proteolytic activity against FITC-casein and Tosyl-Gly-Pro-Arg-AMC is inhibited by the serine proteinase inhibitors PMSF and AMPSF. The protein is also bound by immobilized aminobenzamidine.

Abstract: Dielectric gratings are formed between the word line stacks. Spacers are applied to the sidewalls of the word line stacks and the dielectric gratings. In the openings between the spacers, silicon is epitaxially grown on the upper surfaces of source/drain regions, which are implanted self-aligned to the word line stacks. A silicide is formed on the grown silicon, and a metal layer is applied and structured to form local interconnects, which connect the source/drain regions to upper bit lines.

Abstract: A substantially pure excretory-secretory product is isolatable from Necator americanus and is capable of inducing apoptosis in reactive T cells.

Abstract: The present invention is directed to a method of fabricating a local interconnect. A disclosed method involves forming two separate cavities in the ILD above two electrical contacts of a transistor. A first cavity extend down to an underlying etch stop layer. The first cavity is then filled with a protective layer. The second cavity is then formed adjacent to the first cavity and extends down to expose the underlying etch stop layer. The protective layer is removed to form an expanded cavity including the first and second cavities which expose the underlying etch stop layer in the expanded cavity. The etch stop material in the expanded cavity is also removed to expose an underlying gate contact and expose one of a source or drain contact. The gate contact is then electrically connected with one of the exposed source or drain contacts to form a local interconnect.