Patents by Inventor David Aaron

David Aaron has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10727369
    Abstract: Methods of fabricating a solar cell, and system for electrically coupling solar cells, are described. In an example, the methods for fabricating a solar cell can include forming a first cut portion from a conductive foil. The method can also include aligning the first cut portion to a first doped region of a first semiconductor substrate. The method can include bonding the first cut portion to the first doped region of the first semiconductor substrate. The method can also include aligning and bonding a plurality of cut portions of the conductive foil to a plurality of semiconductor substrates.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: July 28, 2020
    Assignee: SunPower Corporation
    Inventors: Richard Hamilton Sewell, David Aaron Randolph Barkhouse
  • Patent number: 10725930
    Abstract: Aspects of the present disclosure configure a memory sub-system to map logical memory addresses to physical memory addresses using a tree data structure in the memory sub-system. For example, a memory sub-system controller of the memory sub-system can generate a tree data structure on cache memory to cache, from non-volatile memory, at least one portion of mapping data, where the non-volatile memory is implemented by a set of memory components separate from the cache memory. The mapping data, stored on the non-volatile memory, can map a set of logical memory addresses to a corresponding set of physical memory addresses of the non-volatile memory, and a node of the tree data structure can comprise node data that describes a memory area of the non-volatile memory where data is written across a sequence of contiguous physical memory addresses.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventor: David Aaron Palmer
  • Publication number: 20200220031
    Abstract: Methods of fabricating a solar cell, and system for electrically coupling solar cells, are described. In an example, the methods for fabricating a solar cell can include placing conductive wires in a wire guide, where conductive wires are placed over a first semiconductor substrate having first doped regions and second doped regions. The method can include aligning the conductive wires over the first and second doped regions, where the wire guide aligns the conductive wires substantially parallel to the first and second doped regions. The method can include bonding the conductive wires to the first and second doped regions. The bonding can include applying a mechanical force to the semiconductor substrate via a roller or bonding head of the wire guide, where the wire guide inhibits lateral movement of the conductive wires during the bonding.
    Type: Application
    Filed: March 13, 2020
    Publication date: July 9, 2020
    Inventors: Richard Hamilton Sewell, David Aaron Randolph Barkhouse, Nils-Peter Harder, Douglas Rose
  • Publication number: 20200210080
    Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 2, 2020
    Inventors: David Aaron Palmer, Sean L. Manion, Jonathan Parry, Stephen Hanna, Qing Liang, Nadav Grosz, Christian M. Gyllenskog, Kulachet Tanpairoj
  • Publication number: 20200210107
    Abstract: Devices and techniques for arbitrating operation of memory devices in a managed NAND memory system to conform the operation to a power budget. In an example, a method can include enabling a subset of memory die of a memory system having multiple memory die, starting an active timer for each active memory die, initializing execution of a buffered memory command at each active die based on a timestamp associated with the buffered memory command, and disabling a first memory die of the subset of memory die when the active timer for the first die expires to maintain compliance with a power budget of the memory system.
    Type: Application
    Filed: March 5, 2019
    Publication date: July 2, 2020
    Inventor: David Aaron Palmer
  • Publication number: 20200210097
    Abstract: Devices and techniques for generating a response to a host with a memory device are provided. A first command from a host can be executed. A status for the first command can be determined. An inquiry from the host about a second command can be received after execution of the first command has begun. A response can be made to the inquiry that includes information about the second command and the status for the first command.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Nadav Grosz, David Aaron Palmer
  • Publication number: 20200210073
    Abstract: Apparatus and methods are disclosed, including a controller circuit, a volatile memory, a non-volatile memory, and a reset circuit, where the reset circuit is configured to receive a reset signal from a host device and actuate a timer circuit. The timer circuit, where the timer circuit is configured to cause a storage device to reset after a threshold time period. The reset circuit is further configured to actuate the controller circuit to write data stored in the volatile memory to the non-volatile memory before the storage device is reset.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 2, 2020
    Inventor: David Aaron Palmer
  • Publication number: 20200210283
    Abstract: Devices and techniques for extended error correction in a storage device are described herein. A first set of data, that has a corresponding logical address and physical address, is received. A second set of data can be selected based on the logical address. Secondary error correction data can be computed from the first set of data and the second set of data. Primary error correction data can be differentiated from the secondary error correction data by being computed from the first set of data and a third set of data. The third set of data can be selected based on the physical address of the first set of data. The secondary error correction data can be written to the storage device based on the logical address.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventor: David Aaron Palmer
  • Publication number: 20200210108
    Abstract: Devices and techniques for arbitrating operation of memory devices in a managed NAND memory system to conform the operation to a power budget. In an example, a method can include initiating a first plurality of host-requested NAND memory operations of a first type at a first channel of a memory device for a first interval, and, at the completion of the first interval, performing a second plurality of homogeneous, host-requested NAND memory operations of a second type at the first multiple plane memory die for a second interval.
    Type: Application
    Filed: March 5, 2019
    Publication date: July 2, 2020
    Inventor: David Aaron Palmer
  • Publication number: 20200209944
    Abstract: Devices and techniques for arbitrating operation of memory devices in a managed NAND memory system to conform the operation to a power budget. In an example, a method can include receiving an operation change indication for a NAND memory operation at power management circuitry of a NAND memory system, and summing a power credit to a value of a first register associated with the operation change indication to provide an indication of instantaneous power consumption of the NAND memory system as the value of the first register.
    Type: Application
    Filed: March 5, 2019
    Publication date: July 2, 2020
    Inventor: David Aaron Palmer
  • Publication number: 20200210104
    Abstract: Devices and techniques for host adaptive memory device optimization are provided. A memory device can maintain a host model of interactions with a host. A set of commands from the host can be evaluated to create a profile of the set of commands. The profile can be compared to the host model to determine an inconsistency between the profile and the host model. An operation of the memory device can then be modified based on the inconsistency.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Nadav Grosz, David Aaron Palmer
  • Publication number: 20200210279
    Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 2, 2020
    Inventors: Jonathan Parry, Nadav Grosz, David Aaron Palmer, Christian M. Gyllenskog
  • Publication number: 20200201784
    Abstract: Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventor: David Aaron Palmer
  • Publication number: 20200201752
    Abstract: Devices and techniques are disclosed herein for allowing host-based maintenance of a flash memory device. In certain examples, memory write information can be encrypted at the memory device and provided to the host for updating and maintaining memory device maintenance statistics.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Inventor: David Aaron Palmer
  • Publication number: 20200194082
    Abstract: Devices and techniques for enhanced flush transfer efficiency via flush prediction in a storage device are described herein. User data from a user data write can be stored in a buffer. The size of the user data stored in the buffer can be smaller than a write width for a storage device subject to the write. This size difference results in buffer free space. A flush trigger can be predicted. Additional data can be marshaled in response to the prediction of the flush trigger. The size of the additional data is less than or equal to the buffer free space. The additional data can be stored in the buffer free space. The contents of the buffer can be written to the storage device in response to the flush trigger.
    Type: Application
    Filed: February 24, 2020
    Publication date: June 18, 2020
    Inventor: David Aaron Palmer
  • Publication number: 20200195716
    Abstract: The present invention relates to IoT devices existing in a deployed ecosystem. The various computers in the deployed ecosystem are able to respond to requests from a device directly associated with it in a particular hierarchy, or it may seek a response to the request from a high order logic/data source (parent). The logic/data source parent may then repeat the understanding process to either provide the necessary response to the logic/data source child who then replies to the device or it will again ask a parent logic/data sources for the appropriate response. This architecture allows for a single device to make one request to a single known source and potentially get a response back from the entire ecosystem of distributed servers.
    Type: Application
    Filed: February 24, 2020
    Publication date: June 18, 2020
    Inventors: David Aaron Allsbrook, Steven Manweiler, Sanket Deshpande, Martin Pandola
  • Patent number: 10684747
    Abstract: Disclosed herein is a computer implemented method and system for conducting an individualized, virtually moderated, and virtual real time debate. Debating topics and debating rules are defined for the debate. A group of panelists is selected for the debate based on the debating topics. An electronic debating platform is provided to the panelists for receiving one or more key points, responses, and counter-responses contributed by each of the panelists in non real time. The key points, the responses, and the counter-responses are governed by the debating rules. The prerecorded key points, responses, counter-responses, and one or more information components relevant to each of the key points are stringed together in sequence. The debate is presented to a viewer on a multimedia presentation layer. The presentation of the debate is customized by enabling the viewer to selectively navigate through the presentation using the sequenced key points, responses, counter-responses, and information components.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: June 16, 2020
    Inventor: David Aaron Hurwitz
  • Patent number: 10685718
    Abstract: Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums which increase read throughput by introducing a delay prior to issuing a command to increase the chances that read commands can be executed in parallel. Upon receipt of a read command, if there are no other read commands in the command queue for a given portion (e.g., plane or plane group) of the die, the controller can delay issuing the read command for a delay period using a timer. If, during the delay period, an eligible read command is received, the delayed command and the newly received command are both issued in parallel using a multi-plane read. If no eligible read command is received during the delay period, the read command is issued after the delay period expires.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: June 16, 2020
    Assignee: Micron Technnology, Inc.
    Inventor: David Aaron Palmer
  • Publication number: 20200172791
    Abstract: The present invention is related to the obtaining and using of multifunctional foaming compositions with wettability modifying, corrosion inhibitory and inhibitory/dispersants mineral scale properties with high stability in environments of high temperature, high pressure and tolerance to high concentrations of divalent ions such as calcium, magnesium, strontium and barium. The multifunctional foaming compositions are obtained from the combination of supramolecular complexes resulting from interactions of alkyl amido propyl hydroxysultaines and/or alkyl amido propyl betaines and/or alkyl hydroxysultaines and/or alkyl betaines and anionic surfactant of type alkyl hydroxyl sodium sulfonate and alkenyl sulphonates of sodium, with cationic surfactants as tetra-alkyl ammonium halides and copolymers derivatives of itaconic acid/sodium vinyl sulfonate and/or terpolymers derived from itaconic acid/sodium vinyl sulphonate/aconitic acid.
    Type: Application
    Filed: February 5, 2020
    Publication date: June 4, 2020
    Inventors: Raúl HERNÁNDEZ ALTAMIRANO, Luis Silvestre ZAMUDIO RIVERA, Violeta Yázmin MENA CERVANTES, Erick Emanuel LUNA ROJERO, David Aarón NIETO ÁLVAREZ, Rodolfo CISNEROS DEVORA, Mirna PONS JIMÉNEZ, Alejandro RAMÍREZ ESTRADA, América Elizabeth MENDOZA AGUILAR, Sung Jae Ko KIM
  • Publication number: 20200167279
    Abstract: Devices and techniques for enhanced flush transfer efficiency in a storage device are described herein. A flush trigger for a user data write can be identified. Here, user data corresponds to the user data write and was stored in a buffer. The size of the user data stored in the buffer is smaller than a write width for a storage device subject to the write. The difference ins the user data size in the buffer and the write width is buffer free space. Additional data can be marshalled in response to the identification of the flush trigger. Here, the additional data size is less than or equal to the buffer free space. The user data and the additional data can then be written to the storage device.
    Type: Application
    Filed: November 27, 2018
    Publication date: May 28, 2020
    Inventor: David Aaron Palmer