Abstract: Embodiments are provided in which result forwarding for each execution unit in a processor is implemented for only one operand input of the execution unit. If another non-implemented operand input of the execution unit needs forwarded results, the forwarded results are passed through the implemented operand input. Non-forwarded operands are passed through the non-implemented operand input.

Abstract: A method and apparatus for purging a cache line from an issuing processor and sending the cache line to the cache of one or more processors in a multi-processor shared memory computer system. The method and apparatus enables cache line data to be moved from one processor to another before the receiving processor needs the data thus preventing the receiving processor from incurring a cache miss event.

Abstract: Embodiments are provided in which two or more sub-ALUs are interleaved to form a single ALU so as to shorten and reduce the number of the connection lines interconnecting the ALU to other devices.

Abstract: Embodiments are provided in which the generation of a carry of a sum of two numbers can be implemented by adding only some most significant bits of the two numbers and assuming that the sum of the remaining bits do not generate a carry. Other embodiments are also provided in which the generation of the carry of a sum of the two numbers can be implemented using carry look-ahead techniques wherein generate and propagate terms are generated. By combining the product terms of the carry function and combining pairs of propagate or generate terms, the generation of the carry of the sum of the two numbers can be implemented in an And-Or-Inverter function less complex than that of prior art. Still other embodiments are provided in which one operand of a carry generation circuit comes from a fixed source and the other operand is selected from several forwarding sources.

Abstract: An apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit is described. The apparatus and method operating on a first binary number and a second binary number comprise: a first arithmetic logic unit (ALU) operating on a first lower portion of the first binary number and a second lower portion of the second binary number to produce a first result and a carry out signal; and a second ALU operating on a first upper portion of the first binary number and a second upper portion of the second binary number to produce a second result; wherein at least a portion of the pipelined circuit stalls in response to the carry out signal. Another embodiment includes memory comprising a plurality of words, each word comprising data bits and a flag bit indicating a predetermined number of the most significant data bits are all zero.

Abstract: The cabinet cooler has an open housing defined by a lower wall, a rear wall, opposite side walls, and a top wall. The lower wall has a plurality of wheels positioned on a bottom thereof so that the cabinet cooler can be easily moved. The lower wall also has a pair of slots therethrough having flexible seals therein such that a wheeled rack can be rolled into the opening of the housing. A door attached to one of the side walls can close the housing once the rack is wheeled into the housing. A plurality of fans pull air over dry ice cell(s) to cool the air within the housing and force the cooled air over the rack, which can hold a plurality of trays capable of holding food.

Abstract: Embodiments are provided in which a first and second instructions are executed in parallel. A first and a second address are generated according to the first and second instructions, respectively. The first address is used to select a data cache line of a data cache RAM and a first data bank from the data cache line. The second address is used to select a second data bank from the data cache. The first and second data banks are outputted in parallel from the data cache RAM. An instruction pair testing circuit tests the probability of the first and second instructions accessing a same data cache line of the data cache RAM. If it is unlikely that the two instructions will access a same data cache line, the second instruction is refetched and re-executed, and the second data bank is not used.

Abstract: Embodiments are provided in which a first and second instructions are executed in parallel. A first and a second address are generated according to the first and second instructions, respectively. The first address is used to select a data cache line of a data cache RAM and a first data bank from the data cache line. The second address is used to select a second data bank from the data cache. The first and second data banks are outputted in parallel from the data cache RAM. An instruction pair testing circuit tests the probability of the first and second instructions accessing a same data cache line of the data cache RAM. If it is unlikely that the two instructions will access a same data cache line, the second instruction is refetched and re-executed, and the second data bank is not used.

Abstract: The present invention relates to compositions and methods for mitigating corrosion of applied color designs on a bottle, or on another glass or ceramic item. More specifically the composition or method of the present invention can mitigate corrosion even in the presence of a known corrosive agent. The composition and methods of the invention employ one or more phosphates and one or more phosphonates at a ratio that reduces or minimizes corrosion of an applied color design.

Abstract: An auxiliary magnetic trip system for a circuit breaker, the auxiliary magnetic trip system includes a strap configured to conduct a first level of electrical current and a second level of electrical current; a u-shape collar with a first pole face, the u-shape collar disposed around the strap; a trip lever rotatably mounted on an axis; and a holdback system releasably coupled to the trip lever, wherein the holdback system prevents movement of the trip lever at the first level of electrical current and releases the trip lever at the second level of electrical current.

Abstract: An auxiliary magnetic trip system for a circuit breaker, the auxiliary magnetic trip system includes a strap configured to conduct a first level of electrical current and a second level of electrical current; a u-shape collar with a first pole face, the u-shape collar disposed around the strap; a trip lever rotatably mounted on an axis; and a holdback system releasably coupled to the trip lever, wherein the holdback system prevents movement of the trip lever at the first level of electrical current and releases the trip lever at the second level of electrical current.

Abstract: The present invention provides a novel cabinet cooler. The cabinet cooler has an open housing defined by a lower wall, a rear wall, opposite side walls, and a top wall. The lower wall has a plurality of wheels positioned on a bottom thereof so that the cabinet cooler can be easily moved. The lower wall also has a pair of slots therethrough having flexible seals therein such that a wheeled rack can be rolled into the opening of the housing. A door attached to one of the side walls can close the housing once the rack is wheeled into the housing. A plurality of fans pull air over dry ice cell(s) to cool the air within the housing and force the cooled air over the rack, which can hold a plurality of trays capable of holding food.

Abstract: A web-based method of obtaining recorded information based on a pre-defined search criteria includes the steps of receiving search criteria from a user through pull down menus, accessing a centralized database of recorded information, wherein the recorded information is linked to at least one identifier such as an identifier number, and comparing the search criteria with information in the database using identifiers to retrieve the requested information. Boolean logic operators are used to define logical relationships among various search criteria to conduct a more focused search and scheduled searching is used to provide updates of recently published recorded information.

Abstract: A data cache is constructed with the same dimensions as for a conventional n-way associative cache, but is constructed as an (n−1)-way associative cache, so that one associative column of the cache is left unused, although the cache has the same memory array size as a typical n-way associative cache. The extra column of data in the cache is organized as an independent logical translation look-aside buffer (TLB) that is n-way associative. Thus, there is no separate TLB array for the cache, rather, the TLB is contained within the data cache array. In this way, the cache can be implemented with a single chip, and can be of relatively large size, on the order of 8 MB or more.

Abstract: An operating handle assembly is provided having an improved handle engagement arrangement, thereby enabling the operating handle assembly to be adaptable for both human and machine interaction without the requirement of special attachment hardware. An operating handle assembly having a handle base and handle stem can accept a first handle extension suitable for human interaction or a second handle extension suitable for machine interaction. Assembly features provide for proper assembly of the handle extension to the handle stem while maintaining appropriate electrical clearances to live parts. The two part operating handle assembly, handle base with handle stem plus handle extension, provides for improved manufacturability of the host device, whereby the end-use construction of the host device need not be identified until a late point in the production cycle. The host device may be, but is not limited to, a standard circuit breaker, a rotary circuit breaker, a switch, or a disconnect device.

Abstract: A magnetic release system for a circuit breaker, the magnetic release system includes a contact structure; a strap configured to conduct a first level of electrical current and a second level of electrical current; a u-shaped collar having a pole face, the u-shaped collar disposed around the strap; a release lever disposed proximate the pole face, the release lever rotatably mounted on the strap; wherein the release lever is releasably engaged with the contact structure; and wherein the release lever prevents movement of the contact structure at the first level of electrical current and releases the contact structure at the second level of electrical current.

Abstract: An adjustable solenoid having an enclosure containing a winding through which a current is passed. The winding defines an area and a plunger is positioned at one end of the area with a mechanical biasing mechanism for providing a biasing force to the plunger, the mechanical biasing mechanism is secured to the plunger at one end and a support at the other end. A stator having a first threaded portion engaged within a threaded opening of the enclosure causes the stator to travel between a first position and a second position as a rotational force is applied to the stator.

Abstract: An adjustable solenoid having an enclosure containing a winding through which a current is passed. The winding defines an area and a plunger is positioned at one end of the area with a mechanical biasing mechanism for providing a biasing force to the plunger, the mechanical biasing mechanism is secured to the plunger at one end and a support at the other end. A stator having a first threaded portion engaged within a threaded opening of the enclosure causes the stator to travel between a first position and a second position as a rotational force is applied to the stator.

Abstract: A data cache is constructed with the same dimensions as for a conventional n-way associative cache, but is constructed as an (n−1)-way associative cache, so that one associative column of the cache is left unused, although the cache has the same memory array size as a typical n-way associative cache. The extra column of data in the cache is organized as an independent logical translation look-aside buffer (TLB) that is n-way associative. Thus, there is no separate TLB array for the cache, rather, the TLB is contained within the data cache array. In this way, the cache can be implemented with a single chip, and can be of relatively large size, on the order of 8 MB or more.

Abstract: A termination connector for a circuit breaker is disclosed. The termination connector preferably includes a plurality of single pole screw receiving members integrally attached by a molded housing for unitary attachment to a line or load end of a circuit breaker to assist in holding a nut or nut plate adjacent each screw hole in the circuit breaker's terminal straps. The molded housing preferably includes a line of perforations between each single pole screw receiving member so that the correct number of single pole screw receiving members can be retained and the others can be knocked off along the line of perforations. Provisions are disclosed for adaption of the connector to metric or English standard nut hardware. In addition, the termination connector and circuit breaker are provided with mating attachment devices for providing a simple yet secure connection.