Abstract: A method is described for joining electrically conducting members using an apparatus having a pin typically formed of a material harder than the electrically conducting members. The apparatus causes the pin to rotate at high speeds between the electrically conducting members, wherein the rotating pin causes a portion of material from each electrically conducting member to plasticize and solidify a joint. By translating the apparatus along the joint, the pair of electrically conducting members can be joined without requiring the inclusion of additional filler material.

Abstract: A data cache is constructed with the same dimensions as for a conventional n-way associative cache, but is constructed as an (n−1)-way associative cache, so that one associative column of the cache is left unused, although the cache has the same memory array size as a typical n-way associative cache. The extra column of data in the cache is organized as an independent logical translation look-aside buffer (TLB) that is n-way associative. Thus, there is no separate TLB array for the cache, rather, the TLB is contained within the data cache array. In this way, the cache can be implemented with a single chip, and can be of relatively large size, on the order of 8 MB or more.

Abstract: Disclosed is a predictive instruction cache system, and the method it embodies, for a VLIW processor. The system comprises: a first cache; a real or virtual second cache for storing a subset of the instructions in the second cache; and a real or virtual history look-up table for storing relations between first instructions and second instructions in the second cache. If a first instruction is located in a stage of the pipeline, then one of the relations will predict that a second instruction will be needed in the same stage a predetermined time later. The first cache can be physically distinct from the second cache, but preferably is not, i.e., the second cache is a virtual array. The history look-up table can also be physically distinct from the first cache, but preferably is not, i.e., the history look-up table is a virtual look-up table. The first cache is organized as entries.

Abstract: A data processing system, circuit arrangement, integrated circuit device, program product, and method utilize a unique prefetch circuit arrangement that speculatively fetches instructions for execution by a processor based upon history data associated with such instructions. In particular, the history data for a given instruction identifies the next instruction that was executed immediately subsequent to the given instruction. An instruction history cache is utilized in some implementations to store history data representing predicted next instructions for a plurality of instructions stored in a memory, and the instruction history cache is operated concurrently with a secondary instruction cache so that predicted and actual next instructions may be retrieved in parallel. Predicted next instructions are speculatively executed when retrieved from the instruction history cache; however, execution of such instructions is terminated if the predicted and actual next instructions do not match.

Abstract: A bottom vented circuit breaker capable of top-down assembly onto equipment (10) includes a plurality of breaker cassettes (12) disposed in a base (14) with a cover (16) mounted upon the base (14). Breaker cassettes (12) include breaker connection lugs (18) extending therefrom for electrically connecting to equipment connection lugs (20) extending from a protected circuit. Base (14) includes a plurality of discrete arc gas vent structures (56) extending from a bottom wall (52). Each arc gas vent structure (56) comprises a manifold portion (58) in fluid communication with duct portions (60, 62). Ducts (60, 62) extend substantially parallel to each other and outward from manifold (58) along spacers (54) or side walls (44, 46), culminating at exit ports (64, 66). The external surface (74) of ducts (60, 62) are separated by a minimum distance “A” forming access opening (21) in conjunction with side walls (44, 46) and spacers (54).

Abstract: A circuit breaker rotary contact arrangement is disclosed in which the ends of the line and load straps supporting the fixed contacts are hook-shaped to control the angle of the repulsive force exhibited between the fixed contacts and the movable contacts arranged at the opposing ends of the rotary contact arm. The fixed contacts face outwardly away from the central pivot of the contact arm such that a horizontal component of the popping force acts away from the center of rotation keeping the contact arm in tension for avoiding a buckling effect allowing contact arms with smaller cross sectional area to be used to increase contact arm mobility and reduce the cost.

Abstract: A molded case circuit breaker and current suppressing unit protects an electric motor without tripping during motor current reversal. The circuit breaker trip unit provides long time, short time and instantaneous over current protection against abnormal overload and low-current short circuit currents within the protected circuit. The current suppressing unit rapidly suppresses high-current short circuit currents until the circuit breaker responds to isolate the protected equipment.

Abstract: A circuit interrupter of the type including an electronic trip unit for overcurrent determination includes a separate circuit to power the trip unit along with a Hall Effect or GMR Device to sense the current flow within the protected circuit. A removable option plug electrically interconnects with the trip unit to enable ground fault and arcing fault protection.

Abstract: A fault current interrupter is provided by the parallel combination of a polymer current limiter and a voltage dependent resistor connected across a pair of separable contacts to permit the interruption of current without the occurrence of arcing between the contacts when the contacts first become separated. The polymer current limiter is selected to have a relatively low resistance at quiescent operating currents and a substantially higher resistance at short circuit overcurrents. This allows the current to transfer away from the contacts through the polymer current limiter until the voltage across the voltage dependent resistor causes the voltage dependent resistor to become conductive and thereby transfer the current away from the polymer current limiter.

Abstract: In a computer capable of executing a superscalar and a very long instruction word instruction wherein the computer has compiled a number of primitive operations that can be executed in parallel into a single instruction having multiple parcels and each of the parcels correspond to an operation, the invention is an improved instruction cache to store all potential subsequent instructions and a method to select the subsequent instruction when several possible branches of execution are probable and must be evaluated. All branch conditions and all addresses of potential subsequent instructions of an instruction are replicated and stored in the instruction cache. All potential subsequent instructions are stored in the same block of the instruction cache having the same next address; individual instructions are identified by the replicated offset addresses. Further the instruction cache is divided into minicaches, each minicache to store one parcel, which allows rapid autonomous execution of each parcel.

Abstract: A method and apparatus for maintaining coherence between shared data stored within a plurality of memory devices, each memory device residing in a different node within a tightly coupled multiprocessor system. Each node includes a "local coherence unit" and an associated processor. A cache unit is associated with each memory/processor pair. Each local coherence unit maintains a table which indicates whether the most current copy of data stored within the node resides in the local memory, in the local cache, or in a non-local cache. The present invention includes a "global coherence" unit coupled to each node via the logical interconnect. The global coherence unit includes a interconnect monitoring device and a global coherence table. When data which resides within the memory of a first node is transferred to a second node, the interconnect monitoring device updates the global coherence table to indicate that the data is being shared.

Abstract: Systems are provided for saving register data in a pipelined data processing system, and for restoring the data to the appropriate register in the event of an exception condition. One embodiment concerns a latch feedback assembly, such as a SRL, which includes multiple series-connected latches having a feedback connection between last and first latches. The latches are clocked to temporarily reserve a delayed backup copy of data from the first latch on the last latch. Upon detection of an exception, the backup copy is first preserved by disabling writes to the last latch; then the backup copy is copied to the first latch to restore the first latch to its state prior to occurrence of the exception. Another embodiment involves a register file save/restore mechanism, in which an additional bank of registers, called a "backup register", is coupled to a register file. When data is stored in an address of the register file, the address and its data content are also stored in the backup register.

Abstract: A fixed wireless access subscriber unit containing a wireless transceiver and a telephone subscriber line interface circuit which supports privacy and remote release of hold between the subscriber unit and extension telephones are disclosed. The subscriber unit detects when the primary handset, or an extension telephone set goes off-hook. In response the subscriber unit modifies the voltage and/or current characteristics on the telephone subscriber line which connects the extension sets to the subscriber unit in such a manner that extension sets connected to the telephone subscriber line will sense when the primary handset goes off-hook.

Abstract: A lock-down device for use in a circuit breaker assembly. The device comprises a base for releasably securing the device to the assembly's saddle, an arm portion connected to the base, and a hand portion, connected to the arm portion, for engaging the housing of a first circuit breaker such that when the first circuit breaker and a second circuit breaker is mounted on the saddle the hand portion is intermediate the first and second circuit breakers and the first circuit breaker cannot be inadvertently removed from the saddle. In an alternative embodiment, the hand portion of the device comprises flanges for engaging and permitting the lock-down of the second circuit breaker as well.

Abstract: A method and apparatus for processing a character for anti-aliased display on a raster output device. A set of density values is computed for a set of raster positions to represent the character and the density values of the set are scaled to extend their range upward toward a maximum density value, whereby generally at least one of the density values of the set becomes the maximum density value. In one embodiment, the set of density values is computed from a rendering of the character at resolution higher than the resolution of the output device. In another embodiment, the character is created by a font having font metrics including a reference dimension, and the density values are scaled by computing adjusted values as a non-decreasing function of the original values, the function being defined to compute a maximum adjusted density value for at least one non-maximum density value.

Abstract: A high speed pseudo-, 8-, 16-, or greater, ported cache memory, and associated effective address generation scheme. Based upon either two-port building blocks, or twice as many single-port building blocks, which are interleaved, the cache memory is arranged as a functional equivalent to a true 8-, 16-, or greater ported interleaved cache memory.

Abstract: A circuit breaker is equipped with a current limiting arc runner for effective overcurrent interruption without additional heating under quiescent operating conditions. Upon contact separation, an arc is drawn with the endpoints of the arc being initially rooted on the set of open contacts. Further opening of the contacts commutates the arc onto the current limiting arc runner to suppress the circuit current.

Abstract: Systems are provided for saving register data in a pipelined data processing system, and for restoring the data to the appropriate register in the event of an exception condition. One embodiment concerns a latch feedback assembly, such as a SRL, which includes multiple series-connected latches having a feedback connection between last and first latches. The latches are clocked to temporarily reserve a delayed backup copy of data from the first latch on the last latch. Upon detection of an exception, the backup copy is first preserved by disabling writes to the last latch; then the backup copy is copied to the first latch to restore the first latch to its state prior to occurrence of the exception. Another embodiment involves a register file save/restore mechanism, in which an additional bank of registers, called a "backup register", is coupled to a register file. When data is stored in an address of the register file, the address and its data content are also stored in the backup register.

Abstract: Compile and/or run time instruction scheduling is used in a multiprocessing system to reorder memory access instructions such that a strongly consistent programming model is emulated in a fashion transparent to the programmer. The multiprocessing system detects potential shared memory conflicts, avoiding these conflicts by restarting operation of the affected processing unit at a predetermined previous state, previously archived in a rollback register set, and resuming instruction execution from that state.

Abstract: An optical fiber element includes an optical fiber having a numerical aperture ranging from 0.08 to 0.34 and a protective coating affixed to the outer surface of the optical fiber. The protective coating has a Shore D .?.hardnees.!. .Iadd.hardness .Iaddend.value of 65 or more and remains on the optical fiber during connectorization so that the fiber is neither damaged by the blades of a stripping tool nor subjected to chemical or physical attack.