Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data, group a plurality of KV pair data based on a data clustering value, aggregate the grouped plurality of KV pair data, and program the aggregated plurality of KV pair data to the memory device. A length of the KV pair data is less than a size of a flash management unit (FMU). The KV pair data includes a key and a value. Each KV pair data of the plurality of KV pair data has a length less than the size of the FMU. The received KV pair data is stored in a temporary location and grouped together in the temporary location. The grouping is based on a similarity of characteristics of plurality of KV pair data.

Abstract: The present disclosure generally relates partial speed changes to improve in-order data transfer. Rather than determining an ECC decoder on a first available decoder basis, the ECC decoder may be based on the ECC decoder level. A memory device will have at least one FMU that has a syndrome weight (SW). The disclosure proposes assigning FMU's based on the SW rate. At the time the command is read, the data storage device determines which level of decoder will be assigned to the FMU. The determination will then be checked according to different system environment parameters to maintain performance or reduce power consumption. The arrangement allows a more flexible system design that can adapt according to the current system status.

Abstract: Error correction code (ECC) coding for key-value data storage devices. In one embodiment, a controller includes a memory interface configured to interface with a memory; an ECC engine configured to perform ECC coding on data stored in memory; a controller memory including a flash translation layer and a namespace database; and an electronic processor. The electronic processor is configured to receive data to be stored, separate the data into a plurality of sub-code blocks, and allocate parity bits to each sub-code block of the plurality of sub-code blocks.

Abstract: A method for depth mapping includes providing a depth mapping device comprising a projector, which is configured to project a pattern of optical radiation onto a target area over a first field of view about a projection axis, and a camera, which is configured to capture images of the target area within a second field of view, narrower than the first field of view, about a camera axis, which is offset transversely relative to the projection axis. The projector projects the pattern onto first and second planes at first and second distances from the camera, and the camera captures first and second reference images containing first and second parts of the pattern on the first and second planes, respectively. The first and second reference images are combined to produce an extended reference image including both the first and second parts of the pattern.

Abstract: The present disclosure generally relates to improving adaptive tuning of different clock rates of a memory device. Rather than clock rates only being determined off of one parameter such as workload, the clock rates now will be determined using multiple parameters. The tuning may be based on system parameters to allow the system to withstand challenges that arise during the operation. The clock frequency table is maintained in the device controller. The table holds the clock frequency of each component. The disclosure proposes modifying the table according to different system environment parameters to maintain performance or reduce power consumption. Adaptive tuning allows a more flexible system design that can adapt according to the current system status. Adaptive tuning also reduces peak power consumption, improves performance, and better quality of service (QoS) compatibility characteristics.

Abstract: Storage devices are configured to be utilized in a variety of blockchain related activities that rely on a proof of space consensus model. These storage devices are required to process a lot of read and write cycles on their memory devices to generate the desired proof of space consensus data. The generation and storing of this generated data requires very different types of memory device usage. Storage devices may be configured to optimize these different usage types upon detecting these proof of space blockchain activities. These optimizations can include suspending one or more background or other garbage collection activities. Additional optimizations can further include configuring partitions or namespaces to comprise single-level-cell majority or single-level-cell only memory devices to increase writing speeds. Further optimizations can include interleaving or extending the length of error correction codes.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is further configured to receive a key value (KV) pair data, determine a size of a value length and a size of a target wordline of the memory device for programming of the KV pair data, determine a size of residual data, store the residual data in a location separate from the target wordline and the KV pair data minus the residual data to the target wordline, and read the residual data from the location separate and the target wordline data in response to a read command for the KV pair data. The size of the value length is greater than the size of the target wordline. The size of the residual data is the size of the value length minus the size of the target wordline.

Abstract: A storage system supports several memory mappings that translate data bits into different physical voltage levels in its non-volatile memory. The storage system receives a selection of one of the memory mappings from a host, which makes the selection based on an application or expected workload of the host. The storage system uses the selected memory mapping for a memory access operation, such as a read operation or a write operation.

Abstract: Low-density parity-check (LDPC) coding based on memory cell voltage distribution (CVD) in data storage devices. In one embodiment, a memory controller includes a memory interface configured to interface with a non-volatile memory; and a controller. The controller is configured to receive a plurality of data pages to be stored in the non-volatile memory, and transform the plurality of data pages into a plurality of transformed data pages. The controller is further configured to determine a plurality of parity bits based on the plurality of transformed data pages, and store the plurality of data pages and the plurality of parity bits in the non-volatile memory.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a search command from a host device, where the search command is for value associated with a key value (KV) format having a specific sequence, prepare one or more search buffers and send the one or more search buffers to the memory device, retrieve one or more wordlines having KV pair data associated with the KV format, where the KV pair data includes a key and a value, compare the retrieved one or more wordlines with the one or more search buffers for values having the specific sequence, and provide at least a portion of the value from one or more KV pair data based on the comparing to the host device.

Abstract: Before a read threshold is needed to read a wordline in memory, a data storage device can infer a plurality of read thresholds based on possible conditions of the memory that may exist when the read threshold is eventually needed. When the read threshold is needed, it is selected from the previously-inferred read thresholds based on the current conditions of the memory. This can improve latency and throughput, improve quality of service, reduce power consumption, and reduce errors.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to segment a key to physical (K2P) table into two or more segments, wherein each segment of the two or more segments corresponds to a caching priority of key value (KV) pair data, organize the K2P table by storing and relocating one or more K2P table entries into a respective segment of the two or more segments, wherein the storing and relocating comprises moving a K2P table entry based on the caching priority of the KV pair data into the respective segment having the caching priority, and utilize the K2P table to manage KV pair data stored in the memory device, wherein utilizing the K2P table comprises applying a same management operation, such as prefetching, to each K2P table entry of a same segment.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to program key value (KV) pair data to the memory device, where the KV pair data includes a key and a value, analyze the key, and generate metadata based on the analyzing. The controller is further configured to generate a metadata index for a plurality of KV pair data, where the metadata index value corresponds to a similarity or a difference between a first key and a second key, and cluster generated metadata based on the metadata index. The controller is further configured to receive a read command for the KV pair data, analyze the generated metadata of the KV pair data, generate a predicted next key, and use read look ahead (RLA) to read a predicted next KV pair data based on the predicted next key.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data from a host device, where the KV pair data includes a key and a value, determine whether the KV pair data corresponds to a first tier or a second tier, where the second tier has a lower performance requirement than the first tier, and program the value of the KV pair data as padding data when the KV pair data corresponds to the second tier. The determining is based on a received hint of the KV pair data, a relative performance of the KV pair data, and a length of the KV pair data. The controller is configured reclassify the KV pair data based on a read frequency of the KV pair data.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine a health of a plurality of wordlines of a block of a plurality of blocks, receive key value (KV) pair data, select a wordline of the plurality of wordlines based on the health, and program the KV pair data to the selected wordline. The KV pair data includes a value length and a relative performance indicator. The controller is further configured to mark a block of the plurality of blocks due to a high bit error rate (BER) indication, where the marked block is KV operable only. The non-KV pair data stored in the marked block is relocated to a non-marked block.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data from a host device, where the KV pair data includes a key and a value, store the received KV pair data in an intermediate storage location, match the received KV pair data to another one or more KV pair data stored in the intermediate storage location, where the matching is based on a utilization parameter of a storage container of the memory device, aggregate the matched received KV pair data and the another one or more KV pair data stored in the intermediate storage location, and program the aggregated KV pair data to the memory device.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data, determine an entropy value of the received KV pair data, select an error correction code (ECC) code rate based on the determined entropy value, and program the KV pair data to a codeword (CW). The KV pair data includes a key and a value. The programming includes encoding the KV pair data using the selected ECC code rate. The controller is further configured to aggregate a portion of another KV pair data and the KV pair data and program the aggregated KV pair data to the CW using a selected ECC code rate.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data from a host device, where the KV pair data includes a key and a value, determine whether the KV pair data corresponds to a first tier or a second tier, where the second tier has a lower performance requirement than the first tier, and program the value of the KV pair data as padding data when the KV pair data corresponds to the second tier. The determining is based on a received hint of the KV pair data, a relative performance of the KV pair data, and a length of the KV pair data. The controller is configured reclassify the KV pair data based on a read frequency of the KV pair data.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data from a host device, where the KV pair data includes a key and a value, store the received KV pair data in an intermediate storage location, match the received KV pair data to another one or more KV pair data stored in the intermediate storage location, where the matching is based on a utilization parameter of a storage container of the memory device, aggregate the matched received KV pair data and the another one or more KV pair data stored in the intermediate storage location, and program the aggregated KV pair data to the memory device.

Abstract: A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a storage system is configured to use a binary full-depth symmetrically-sorted tree to infer a read threshold based on a plurality of parameters of the memory.