Patents by Inventor DAVID AVRAHAM

DAVID AVRAHAM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12353744
    Abstract: Storage devices are configured to be utilized in a variety of blockchain related activities that rely on a proof of space consensus model. These storage devices are required to process a lot of read and write cycles on their memory devices to generate the desired proof of space consensus data. The generation and storing of this generated data requires very different types of memory device usage. Storage devices may be configured with a first partition for high-speed access for generating the data, while a second partition is also configured for long-term storage of the generated data. As memory devices reach their estimated end-of-life, they can be dynamically reassigned to the second partition. Likewise, some storage devices may be equipped with multiple memory arrays of different types of memory devices. One set of memory devices can be used for generation, while cheaper, write-once or few memory devices are provided for storage.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: July 8, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: David Avraham, Alexander Bazarsky, Ran Zamir
  • Publication number: 20250199903
    Abstract: A data storage device includes an error correction code (ECC) system and a decoder gear determination system. The decoder gear determination system dynamically enhances error correction capabilities of a decoder of the ECC system should the decoder fail to decode a codeword. The decoder gear determination system enhances the error correction capabilities of the decoder prior to initiating a gear switch, in which another decoder, with higher error correction capabilities, is used to decode the codeword. The decoder gear determination system enhances the error correction capabilities of the decoder by deriving information about the failed decoding attempt. The derived information is used to generate an updated decoding parameter that is provided to the decoder. The decoder attempts a subsequent decoding process on the codeword using the updated decoding parameter.
    Type: Application
    Filed: December 19, 2023
    Publication date: June 19, 2025
    Inventors: David Avraham, Ran Zamir, Eran Sharon
  • Patent number: 12326805
    Abstract: A DNA-based storage system uses a set of initial state transition probabilities during a decoding process in which a DNA codeword is decoded. After a threshold number of decoding iterations of the decoding process have been executed, at least one initial state transition probability of the set of initial state transition probabilities is updated. The at least one initial state transition probability is updated based, at least in part, on information obtained during the threshold number of decoding iterations. When the at least one initial state transition probability is updated, the decoding process resumes and uses the updated at least one initial state transition probability.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: June 10, 2025
    Assignee: Western Digital Technologies, Inc.
    Inventors: David Avraham, Ran Zamir, Alexander Bazarsky
  • Publication number: 20250183915
    Abstract: A DNA-based storage system implements a sub-code architecture for error correction capability (ECC) purposes. The sub-code architecture enables a long DNA strand to be divided into two or more short DNA strands. Each short DNA strand has its own unique parity information. Additionally, each short DNA strand is separately decodable from the other short DNA strands. The parity information associated with a particular short DNA strand is used to correct any errors that occur or are detected during the decoding process. However, if the decoding and error correction processes are not successful using the parity information associated with the particular short DNA strand, global parity information is used to decode the particular short DNA strand and correct the errors. Global parity information includes information from each short DNA strand and the parity information associated with each short DNA strand.
    Type: Application
    Filed: December 4, 2023
    Publication date: June 5, 2025
    Inventors: Alexander Bazarsky, Ran Zamir, David Avraham
  • Publication number: 20250174272
    Abstract: A state transition matrix for a data storage system indicates a reliability of data that was read or decoded from a data storage channel. The state transition matrix includes a probability of reading each state of a nucleotide base in an identified storage material when that nucleotide base was initially programmed in a particular state. The state transition matrix is generated by identifying a storage material with the most copies in the data storage system. During a sequencing process, the identified storage material is decoded, corrected and compared against the storage material that was originally synthesized. This information is used to determine the probability values for the state transition matrix. The state transition matrix is provided to an error correction system of the data storage system, which uses the probability information when determining whether decoded data of other storage materials should be corrected.
    Type: Application
    Filed: November 29, 2023
    Publication date: May 29, 2025
    Inventors: Ran Zamir, David Avraham, Alexander Bazarsky
  • Patent number: 12293796
    Abstract: A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a storage system is configured to use a binary full-depth symmetrically-sorted tree to infer a read threshold based on a plurality of parameters of the memory.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: May 6, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Eran Sharon, Ariel Navon, Alexander Bazarsky, David Avraham, Nika Yanuka, Idan Alrod
  • Patent number: 12283328
    Abstract: A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: April 22, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Eran Sharon, Ariel Navon, Alexander Bazarsky, David Avraham, Nika Yanuka, Idan Alrod, Tsiko Shohat Rozenfeld, Ran Zamir
  • Publication number: 20250117037
    Abstract: Different operations have different clock rate bottleneck points. For example, during a read operation, the processors may be the bottleneck whereas other operations will not be bottlenecks. Those other operations can have their clock rates reduced to save power since there is no benefit to a higher clock rate as the bottleneck is elsewhere. Predicting the bottleneck would be beneficial. Statistics correlating the bottleneck points with the workload and clock rates are tracked. When the workload changes, the statistics can be consulted to determine where the bottleneck is located and then slow down the clock rates for the non-bottleneck operations. A clock rate table is maintained in the device controller. The table holds the clock rate of each component. Predicting the workload and hence, the clock rates, reduces power consumption, improves performance, and better quality of service (QOS) compatibility characteristics.
    Type: Application
    Filed: October 9, 2023
    Publication date: April 10, 2025
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shay BENISTY, Ariel NAVON, Alexander BAZARSKY, Dudy David AVRAHAM
  • Publication number: 20250078930
    Abstract: A data storage device has an inference engine that can infer a read threshold based on a non-linear function of inputs that reflect current memory and data conditions. The read threshold can be used in reading a wordline in the memory. Using a machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and also improve latency, throughput, power consumption, and quality of service.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 6, 2025
    Applicant: Western Digital Technologies, Inc.
    Inventors: David Avraham, Ariel Navon, Alexander Bazarsky, Eran Sharon
  • Publication number: 20250036814
    Abstract: Key value (KV) pair data includes a key and a value, where the key addresses the value. The value may include one or more flash management units (FMUs). Because the value is read in order, sequentially from one FMU to a next FMU, end-to-end (E2E) protection of the value may be optimized and improved. E2E protection may including using checksum signatures, of which cyclic redundancy code (CRC) signatures are but one example, to ensure that corrupted data is not returned to a host device. Optimizing checksum signatures used to protect the value may include generating an aggregated checksum signature for each FMU based on a current FMU and each previous FMU of the value or only generating a single checksum signature for an entirety of the value. Thus, characteristics of the value may be taken advantage of in order to improve and optimize E2E protection.
    Type: Application
    Filed: July 26, 2023
    Publication date: January 30, 2025
    Applicant: Western Digital Technologies, Inc.
    Inventors: Alexander BAZARSKY, David AVRAHAM, Ran ZAMIR
  • Publication number: 20250015599
    Abstract: A method may include: applying a first voltage on at least one first terminal of a first direct current (DC) bus electrically connected to a power source, obtaining at least one indication that discharge of a second voltage related to the first voltage should be performed, and discharging the second voltage by electrically connecting at least one second terminal of a second DC bus to a ground in response to the at least one indication. Another method may include: injecting a current at at least one terminal of a direct current (DC) bus that is electrically connected to a power source, simultaneous to injecting the current, measuring an insulation relative to ground, obtaining an electrical parameter related to the power source, and, in response to the electrical parameter, maintaining the current injected at the terminal of the DC bus without ceasing the measuring of the insulation relative to a ground.
    Type: Application
    Filed: September 25, 2024
    Publication date: January 9, 2025
    Inventors: Ilan Yoscovich, Liron Har-Shai, Amir Grossberg, Matan Atias, Daniel Zmood, David Avraham
  • Patent number: 12166505
    Abstract: A data storage device with partial speed changes to improve in-order data transfer. Rather than determining an ECC decoder on a first available decoder basis, the ECC decoder may be based on the ECC decoder level. A memory device will have at least one FMU that has a syndrome weight (SW). The disclosure proposes assigning FMU's based on the SW rate. At the time the command is read, the data storage device determines which level of decoder will be assigned to the FMU. The determination will then be checked according to different system environment parameters to maintain performance or reduce power consumption. The arrangement allows a more flexible system design that can adapt according to the current system status.
    Type: Grant
    Filed: October 25, 2023
    Date of Patent: December 10, 2024
    Assignee: Sandisk Technologies, Inc.
    Inventors: Shay Benisty, Ariel Navon, Alexander Bazarsky, David Avraham
  • Patent number: 12142926
    Abstract: A method may include: applying a first voltage on at least one first terminal of a first direct current (DC) bus electrically connected to a power source, obtaining at least one indication that discharge of a second voltage related to the first voltage should be performed, and discharging the second voltage by electrically connecting at least one second terminal of a second DC bus to a ground in response to the at least one indication. Another method may include: injecting a current at least one terminal of a direct current (DC) bus that is electrically connected to a power source, simultaneous to injecting the current, measuring an insulation relative to ground, obtaining an electrical parameter related to the power source, and, in response to the electrical parameter, maintaining the current injected at the terminal of the DC bus without ceasing the measuring of the insulation relative to a ground.
    Type: Grant
    Filed: August 17, 2023
    Date of Patent: November 12, 2024
    Assignee: Solaredge Technologies Ltd.
    Inventors: Ilan Yoscovich, Liron Har-Shai, Amir Grossberg, Matan Atias, Daniel Zmood, David Avraham
  • Patent number: 12124288
    Abstract: Storage devices are configured to be utilized in a variety of blockchain related activities that rely on a proof of space consensus model. These storage devices are required to process a lot of read and write cycles on their memory devices to generate the desired proof of space consensus data. The generation and storing of this generated data require very different types of memory device usage. As these operations increase in popularity, the need to segment storage devices meant for proof of space usage and those which are not becomes more important. Storage devices may be configured to throttle these different usage types upon detecting these proof of space blockchain activities. Throttling may include reducing clock frequencies, selecting slower performing trim parameters, and programming memory devices with a reduced voltage window, among other processes. Detecting whether throttling should commence, or end can be done via a deployed machine learning classifier.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: October 22, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ran Zamir, David Avraham, Alexander Bazarsky
  • Patent number: 12112048
    Abstract: The present disclosure generally relates to improving adaptive tuning of different clock rates of a memory device. Rather than clock rates only being determined off of one parameter such as workload, the clock rates now will be determined using multiple parameters. The tuning may be based on system parameters to allow the system to withstand challenges that arise during the operation. The clock frequency table is maintained in the device controller. The table holds the clock frequency of each component. The disclosure proposes modifying the table according to different system environment parameters to maintain performance or reduce power consumption. Adaptive tuning allows a more flexible system design that can adapt according to the current system status. Adaptive tuning also reduces peak power consumption, improves performance, and better quality of service (QoS) compatibility characteristics.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: October 8, 2024
    Assignee: Sandisk Technologies, Inc.
    Inventors: Shay Benisty, Ariel Navon, Alexander Bazarsky, David Avraham
  • Patent number: 12093558
    Abstract: The present disclosure generally relates to estimating when data to be written will be read or re-written prior to actually writing the data to the memory device. The estimating can be used to smartly route the data to the appropriate memory location at the writing stage or to evict the data from a hot memory location to a colder memory location. To perform the estimating, typical traces or data may be used as may the metadata of the data. Separating data according to the data “temperature” (i.e. the expected access time and frequency), and usage to optimize the SLC partition usage has meaningful impact on several storage metrics such as performance and endurance.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: September 17, 2024
    Assignee: Sandisk Technologies, Inc.
    Inventors: Ariel Navon, Idan Alrod, David Avraham, Eran Sharon, Vered Kelner
  • Patent number: 12067268
    Abstract: A data storage device and method for dynamic prediction of random read with low memory consumption are provided. In one embodiment, a data storage device comprises a volatile memory, a non-volatile memory, and a controller. The controller is configured to allocate an amount of space in the volatile memory for a history pattern matcher data structure used to predict next read commands from a host to read data stored in the non-volatile memory; determine an accuracy of the predicted next read commands; and based on the determined accuracy, dynamically allocate a different amount of space in the volatile memory for the history pattern matcher data structure. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: August 20, 2024
    Assignee: Sandisk Technologies, Inc.
    Inventors: Gadi Vishne, Ariel Navon, David Avraham
  • Publication number: 20240193037
    Abstract: A DNA-based storage system includes an error correction system operable to: (a) identify a DNA codeword from a DNA sequencing operation; (b) calculate an initial syndrome weight; (c) determine that the initial syndrome weight is greater than a predetermined threshold; (d) perform an alignment alteration in the information segment by: (i) selecting a skew point within the information segment; (ii) performing an indel operation on the information segment at the skew point; (iii) calculating a modified syndrome weight; (iv) comparing the initial syndrome weight with the modified syndrome weight; and (v) incorporating the indel operation into the information segment when the comparing indicates an improvement in the modified syndrome weight; (e) decode the modified codeword; and (f) transmit the contents of the output file to a computing device, the output file representing user data stored within the DNA molecule.
    Type: Application
    Filed: July 20, 2023
    Publication date: June 13, 2024
    Inventors: David Avraham, Ran Zamir, Alexander Bazarsky
  • Publication number: 20240185021
    Abstract: A computer-implemented method includes receiving an encoding table defining a plurality of mappings between input segments and encoded segments, where each encoded segment defines an ordered string of data representing a sequence of one or more deoxyribonucleic acid (DNA) nucleotide bases; identifying an input string of input data; segmenting the input string into a plurality of input tuples; for each input tuple, generate a plurality of encoded tuples by identifying an entry of the encoding table that has an input segment equal to the input tuple and adding an encoded tuple that includes an encoded segment; converting the plurality of encoded tuples into a DNA sequence string of DNA nucleotides by concatenating the plurality of encoded tuples in an order defined by the plurality of input tuples; and transmitting the DNA sequence string of DNA nucleotides to be used for synthesizing at least one DNA molecule.
    Type: Application
    Filed: July 19, 2023
    Publication date: June 6, 2024
    Inventors: Ran Zamir, Alexander Bazarsky, David Avraham
  • Publication number: 20240185940
    Abstract: Technology is disclosed herein for memory health monitoring and mitigation based on decoding statistics. Decoding a frame results in a decoding metric (syndrome weight, fail bit count) for that frame. The system tracks a statistic for different sets of frames. The statistic for a set is based on the decoding metrics for that set. The frames may be assigned to sets based on read reference voltages used to read frames or the physical location of the memory cells that store the frames. Memory health mitigation may be performed based on the decoding statistics. One example mitigation is to modify the read reference voltages for the set. Another example mitigation is to trigger reading at soft bit reference levels for a block. Another example mitigation is to trigger direct look ahead reading for a block. Still another example mitigation is to add a block to list of candidates for data refresh.
    Type: Application
    Filed: July 25, 2023
    Publication date: June 6, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shabtay Yudkovich, David Avraham, Mahim Raj Gupta