Abstract: Data storage devices, such as solid state drives (SSDs), are disclosed. A read threshold calibration operation is utilized to generate a calibrated read threshold for one or more voltage states of a cell of a MLC memory. A single-level cell (SLC) read is then executed to sense the ratio of bit values at the read thresholds of the voltage states, where SLC read refers to reading at a single read threshold, rather than to the cell type. The sensing results in a binary page with certain statistics of 1's and 0's. The ratio of 1's (or 0's) in the binary page is used to determine a deviation from the expected ratio, where the deviation is used to adjust the calibrated read threshold to match the voltage states of the MLC memory.

Abstract: Storage devices are configured to be utilized in a variety of blockchain related activities that rely on a proof of space consensus model. These storage devices are required to process a lot of read and write cycles on their memory devices to generate the desired proof of space consensus data. The generation and storing of this generated data requires very different types of memory device usage. Storage devices may be configured with a first partition for high-speed access for generating the data, while a second partition is also configured for long-term storage of the generated data. As memory devices reach their estimated end-of-life, they can be dynamically reassigned to the second partition. Likewise, some storage devices may be equipped with multiple memory arrays of different types of memory devices. One set of memory devices can be used for generation, while cheaper, write-once or few memory devices are provided for storage.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to store a plurality of codewords in the memory device. Each codeword of the plurality of codewords includes host data and parity data corresponding to the host data. Less than all of the plurality of codewords further includes statistics corresponding to the host data. Each statistic of the plurality of codewords is the same or different as another statistic of the plurality of codewords. The statistics are either incremental statistics, adaptive statistics, or both incremental statistics and adaptive statistics.

Abstract: A data storage device includes a housing and an indicator coupled to the housing. The indicator is configured to indicate a health and/or life stage of the data storage device and operate in the absence of an external power source. The indicator is an electrophoretic display or includes a thermochromic material. The electrophoretic display includes a single indication. The electrophoretic display is a scaling bar. The indicator is coupled to a controller. The controller is configured to calculate a health parameter of the data storage device, determine that that the health parameter has exceeded a threshold, and cause the indicator change from a first state to a second state.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine an error correction code (ECC) code length for KV pair data and/or an ECC code rate for the KV pair data, where the ECC code length and the ECC code rate are selected according to a value length and decoding capability of the KV pair data, generate ECC parity based on the selecting, and program the KV pair data and the generated ECC parity to the memory device.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine a health of a plurality of wordlines of a block of a plurality of blocks, receive key value (KV) pair data, select a wordline of the plurality of wordlines based on the health, and program the KV pair data to the selected wordline. The KV pair data includes a value length and a relative performance indicator. The controller is further configured to mark a block of the plurality of blocks due to a high bit error rate (BER) indication, where the marked block is KV operable only. The non-KV pair data stored in the marked block is relocated to a non-marked block.

Abstract: Low-density parity-check (LDPC) coding based on memory cell voltage distribution (CVD) in data storage devices. In one embodiment, a memory controller includes a memory interface configured to interface with a non-volatile memory; and a controller. The controller is configured to receive a plurality of data pages to be stored in the non-volatile memory, and transform the plurality of data pages into a plurality of transformed data pages. The controller is further configured to determine a plurality of parity bits based on the plurality of transformed data pages, and store the plurality of data pages and the plurality of parity bits in the non-volatile memory.

Abstract: A data storage device includes a memory device including a plurality of endurance groups and a controller coupled to the memory device. The controller is configured to allocate tokens to the plurality of endurance groups, determine whether endurance group has sufficient tokens to perform an operation, and either deny the operation or approve the operation. The operation is selected from the group consisting of: garbage collection, relocation of data, and read scrubbing. Each operation has the same or different cost as another operation. The controller is further configured to set thresholds for each endurance group of the plurality of endurance groups and adjust a threshold for one or more endurance groups of the plurality of endurance groups. The controller is further configured to determine whether the operation will breach quality of service for other endurance groups.

Abstract: Interleaved ECC coding for key-value data storage devices. In one embodiment, a controller includes a memory interface including a namespace database; an ECC engine; a controller memory; and an electronic processor. The electronic processor is configured to receive a host write command, determine whether write access was setup as a key-value (KV) namespace in the namespace database and is associated with the host write command, and control the ECC engine and the memory interface to perform one or more program operations on the data in the memory using the interleaved ECC coding and based on the host write command in response to determining that the write access was setup as the KV namespace in the namespace database and the KV namespace is associated with the host write command.

Abstract: A data storage device includes a memory device including a plurality of endurance groups and a controller coupled to the memory device. The controller is configured to allocate tokens to the plurality of endurance groups, determine whether endurance group has sufficient tokens to perform an operation, and either deny the operation or approve the operation. The operation is selected from the group consisting of: garbage collection, relocation of data, and read scrubbing. Each operation has the same or different cost as another operation. The controller is further configured to set thresholds for each endurance group of the plurality of endurance groups and adjust a threshold for one or more endurance groups of the plurality of endurance groups. The controller is further configured to determine whether the operation will breach quality of service for other endurance groups.

Abstract: A data storage device includes a memory device having a plurality of endurance groups and a controller coupled to the memory device. The controller includes at least one decoder or at least one decoder group. The controller is configured to allocate a plurality of tokens to each endurance group of the plurality of endurance groups, receive a payment of tokens from an endurance group to access the at least one decoder or the at least one decoder group, and grant access to the at least one decoder or the at least one decoder group to the endurance group based on the payment of tokens. Each decoder or each decoder group is associated with the same or different payment of tokens and each endurance group has a maximum capacity of tokens.

Abstract: A method and apparatus for content aware decoding utilizes a pool of decoders shared data statistics. Each decoder generates statistical data of content it decodes and provides these statistics to a joint statistics pool. As codewords arrive at the decoder pool, the joint statistics are utilized to estimate or predict any corrupted or missing bit values. Codewords may be assigned to a specific decoder, such as a tier 1 decoder, a tier 2 decoder, or a tier 3 decoder, based on a syndrome weight or a bit error rate. The assigned decoder updates the joint statistics pool after processing the codeword. In some embodiments, each decoder may additionally maintain local statistics regarding codewords, and use the local statistics when there is a statistically significant mismatch between the local statistics and the joint statistics pool.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command form a host device, collect environment data of the memory device, decode data associated with the read command, determine a bit error rate (BER) of the decoded data, compare the BER to a threshold, and determine whether the data associated with the read command is to be relocated. The environment data includes temperature, number of program/erase cycles, amount of grown defects, number of past relocations and time since last data relocation. The controller is further configured to dynamically adjust the threshold based on the collected environment data and an amount of time that has passed since a last relocation of the read command data.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to create a dual parity matrix. The dual parity matrix includes a full parity form that includes a payload, a first parity portion, and a second parity portion and a reduced parity form that includes the payload and the first parity portion. The second parity portion is 0. The controller is further configured to create an incremental parity construction matrix. The incremental parity construction matrix includes two arrays. A first array includes a first payload portion, a first, first parity portion, and a first, second parity portion and a second array includes a second payload portion, a second, first parity portion, and a second, second parity portion. The incremental parity construction matrix is arranged in either a block triangular construction or a block diagonal construction.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command form a host device, collect environment data of the memory device, decode data associated with the read command, determine a bit error rate (BER) of the decoded data, compare the BER to a threshold, and determine whether the data associated with the read command is to be relocated. The environment data includes temperature, number of program/erase cycles, amount of grown defects, number of past relocations and time since last data relocation. The controller is further configured to dynamically adjust the threshold based on the collected environment data and an amount of time that has passed since a last relocation of the read command data.

Abstract: A memory controller including, in one implementation, a memory interface and a control circuit. The memory interface is configured to receive a punctured codeword read from a non-volatile memory. The control circuit is configured to determine error probability values for a plurality of check nodes associated with a punctured bit included in the punctured codeword. The control circuit is also configured to determine an error probability value for the punctured bit based on the error probability values for the plurality of check nodes associated with the punctured bit and a variable degree associated with the punctured bit. The control circuit is further configured to determine a log likelihood ratio (LLR) value for the punctured bit based on the error probability value for the punctured bit. The control circuit is also configured to decode the punctured codeword using the LLR value for the punctured bit.

Abstract: A memory controller that includes, in one implementation, a memory interface and a controller circuit. The memory interface is configured to interface with a non-volatile memory. The controller circuit is configured to receive a skewed codeword read from the non-volatile memory. The controller circuit is also configured to scan the skewed codeword by inserting or removing a quantity of bits at different locations in the skewed codeword and determining resulting syndrome weights of the skewed codeword. The controller circuit is further configured to determine an adjusted codeword by inserting or removing the quantity of bits at one of the different locations in the skewed codeword which results in a smallest syndrome weight. The controller circuit is also configured to decode the adjusted codeword.

Abstract: The present disclosure generally relates to data storage devices, such as solid state drives (SSDs), and efficient data storage device operations related to power loss incidents. A controller of the data storage device is configured to periodically pre-encode data that is stored in random access memory (RAM), detect a power loss event, and program the data and parity data to non-volatile memory (NVM) in response to detecting the power loss event. Upon reaching a threshold size, the data in RAM may be pre-encoded and the pre-encoded data can be programmed to the RAM or the NVM. The parity data may be stored in one or more locations of the NVM. Upon detecting a power loss event, any data remaining in RAM that is not pre-encoded is encoded. The data and any parity data not yet programmed to the NVM are programmed to the NVM.

Abstract: Fast verification of data integrity of non-volatile memory cells is disclosed. In one aspect, an estimate is made of a bit error rate (BER) associated with the data to be verified without fully decoding the data. If the estimated BER is below a threshold, then the storage system reports that the data meets a data integrity criterion. If the estimated BER is above the threshold, the storage system may decode the data to determine a BER and report whether the data meets the data integrity criterion based on the determined BER. The estimate of the BER may be based on a syndrome weight of the data, a BER of an XOR codeword formed from multiple codewords of the data, or a BER of a sample of the data. Hence, considerable time and power are saved verifying data integrity, at least when the data is not fully decoded.

Abstract: The present disclosure generally relates to data storage devices, such as solid state drives (SSDs). A read threshold calibration operation is utilized to generate a calibrated read threshold for one or more voltage states of a cell of a MLC memory. A single-level cell (SLC) read is then executed to sense the ratio of bit values at the read thresholds of the voltage states, where SLC read refers to reading at a single read threshold, rather than to the cell type. The sensing results in a binary page with certain statistics of 1's and 0's. The ratio of 1's (or 0's) in the binary page is used to determine a deviation from the expected ratio, where the deviation is used to adjust the calibrated read threshold to match the voltage states of the MLC memory.