Abstract: Fast verification of data integrity of non-volatile memory cells is disclosed. In one aspect, an estimate is made of a bit error rate (BER) associated with the data to be verified without fully decoding the data. If the estimated BER is below a threshold, then the storage system reports that the data meets a data integrity criterion. If the estimated BER is above the threshold, the storage system may decode the data to determine a BER and report whether the data meets the data integrity criterion based on the determined BER. The estimate of the BER may be based on a syndrome weight of the data, a BER of an XOR codeword formed from multiple codewords of the data, or a BER of a sample of the data. Hence, considerable time and power are saved verifying data integrity, at least when the data is not fully decoded.

Abstract: A method and apparatus for content aware decoding utilizes a pool of decoders shared data statistics. Each decoder generates statistical data of content it decodes and provides these statistics to a joint statistics pool. As codewords arrive at the decoder pool, the joint statistics are utilized to estimate or predict any corrupted or missing bit values. Codewords may be assigned to a specific decoder, such as a tier 1 decoder, a tier 2 decoder, or a tier 3 decoder, based on a syndrome weight or a bit error rate. The assigned decoder updates the joint statistics pool after processing the codeword. In some embodiments, each decoder may additionally maintain local statistics regarding codewords, and use the local statistics when there is a statistically significant mismatch between the local statistics and the joint statistics pool.

Abstract: A method may include: applying a first voltage on at least one first terminal of a first direct current (DC) bus electrically connected to a power source, obtaining at least one indication that discharge of a second voltage related to the first voltage should be performed, and discharging the second voltage by electrically connecting at least one second terminal of a second DC bus to a ground in response to the at least one indication. Another method may include: injecting a current at at least one terminal of a direct current (DC) bus that is electrically connected to a power source, simultaneous to injecting the current, measuring an insulation relative to ground, obtaining an electrical parameter related to the power source, and, in response to the electrical parameter, maintaining the current injected at the terminal of the DC bus without ceasing the measuring of the insulation relative to a ground.

Abstract: A memory controller including, in one implementation, a memory interface and a control circuit. The memory interface is configured to receive a punctured codeword read from a non-volatile memory. The control circuit is configured to determine error probability values for a plurality of check nodes associated with a punctured bit included in the punctured codeword. The control circuit is also configured to determine an error probability value for the punctured bit based on the error probability values for the plurality of check nodes associated with the punctured bit and a variable degree associated with the punctured bit. The control circuit is further configured to determine a log likelihood ratio (LLR) value for the punctured bit based on the error probability value for the punctured bit. The control circuit is also configured to decode the punctured codeword using the LLR value for the punctured bit.

Abstract: A method may include: applying a first voltage on at least one first terminal of a first direct current (DC) bus electrically connected to a power source, obtaining at least one indication that discharge of a second voltage related to the first voltage should be performed, and discharging the second voltage by electrically connecting at least one second terminal of a second DC bus to a ground in response to the at least one indication. Another method may include: injecting a current at at least one terminal of a direct current (DC) bus that is electrically connected to a power source, simultaneous to injecting the current, measuring an insulation relative to ground, obtaining an electrical parameter related to the power source, and, in response to the electrical parameter, maintaining the current injected at the terminal of the DC bus without ceasing the measuring of the insulation relative to a ground.

Abstract: A method and apparatus for obtaining data from a memory, estimating a probability of data values of the obtained data based on at least one of a source log-likelihood ratio and a channel log-likelihood ratio, wherein each bit in the obtained data has an associated log-likelihood ratio, determining at least one data pattern parameter for the data and performing a decoding process using the at least one data pattern parameters to determine a decoded data set.

Abstract: A method and apparatus for obtaining data from a memory, estimating a probability of data values of the obtained data based on at least one of a source log-likelihood ratio and a channel log-likelihood ratio, wherein each bit in the obtained data has an associated log-likelihood ratio, determining at least one data pattern parameter for the data and performing a decoding process using the at least one data pattern parameters to determine a decoded data set.

Abstract: A method and apparatus for a CTC data copy operation, in that modification, and subsequent encoding only affects a small portion of metadata associated with copied data. By modifying and re-encoding only this small portion of metadata, a small portion of the parity data for the copied data requires updating. In embodiments where there are no errors in the read data to be copied (e.g., from an SLC portion of a NAND), decoding, modification, and encoding, may be done in parallel. Because such a small number of metadata bits are modified, in some embodiments, all possible codewords for the parity bits may be predetermined and combined (e.g., by XOR) to update the metadata parity bits.

Abstract: A memory controller that includes, in one implementation, a memory interface and a controller circuit. The memory interface is configured to interface with a non-volatile memory. The controller circuit is configured to receive a skewed codeword read from the non-volatile memory. The controller circuit is also configured to scan the skewed codeword by inserting or removing a quantity of bits at different locations in the skewed codeword and determining resulting syndrome weights of the skewed codeword. The controller circuit is further configured to determine an adjusted codeword by inserting or removing the quantity of bits at one of the different locations in the skewed codeword which results in a smallest syndrome weight. The controller circuit is also configured to decode the adjusted codeword.

Abstract: An illustrative embodiment of this disclosure is an apparatus, including a memory, a processor in communication with the memory, and a decoder. The processor is configured to train a classifier, calculate one or more features of a codeword, predict an outcome of decoding the codeword with the decoder, and determine, using the classifier, whether the outcome satisfies a predetermined threshold. In some embodiments, based on the outcome, the processor selects a set of decoder parameters to improve decoder performance.

Abstract: Examples described herein relate generally to content aware bit flipping decoders. An example device includes a decoder. The decoder is configured to: process one or more flip thresholds based on statistics of data to be decoded; and perform a bit flipping algorithm on the data using the one or more processed flip thresholds. Other examples relate to methods of processing one or more flip thresholds based on statistics of data to be decoded and performing a bit flipping algorithm on the data using the one or more processed flip thresholds.

Abstract: Examples described herein relate generally to content aware bit flipping decoders. An example device includes a decoder. The decoder is configured to: process one or more flip thresholds based on statistics of data to be decoded; and perform a bit flipping algorithm on the data using the one or more processed flip thresholds. Other examples relate to methods of processing one or more flip thresholds based on statistics of data to be decoded and performing a bit flipping algorithm on the data using the one or more processed flip thresholds.

Abstract: An illustrative embodiment of this disclosure is an apparatus, including a memory, a processor in communication with the memory, and a decoder. The processor is configured to train a classifier, calculate one or more features of a codeword, predict an outcome of decoding the codeword with the decoder, and determine, using the classifier, whether the outcome satisfies a predetermined threshold. In some embodiments, based on the outcome, the processor selects a set of decoder parameters to improve decoder performance.

Abstract: A method for punctured bit estimation includes receiving a punctured codeword. The method further includes generating a reconstructed codeword using the punctured codeword and at least one punctured bit having a default logic value. The method further includes generating a syndrome vector for the reconstructed codeword. The method further includes determining, using the syndrome vector, a number of unsatisfied parity-checks for the at least one punctured bit. The method further includes determining, for the at least one punctured bit, a bit value using, at least, the number of unsatisfied parity-checks associated with the at least one punctured bit.

Abstract: Disclosed herein are memory devices, systems, and methods of content-aware decoding of encoded data. In one aspect, an encoded data chunk is received and one or more characteristics, such as source statistics, are determined. A similar data chunk (that may, e.g., contain data of a similar type) with comparable statistics may be sought. The similar data chunk may, for example, have source statistics that are positively correlated to the source statistics of the encoded data chunk to be decoded. Decoder parameters for the encoded data may be set to correspond with decoder parameters suited to the similar data chunk. The encoded data chunk is decoded using the new decoder parameters. Decoding encoded data based on content can enhance performance, reducing decoding latency and/or power consumption.

Abstract: A storage device may include a decoder configured to connect bits to a content node based on content-aware decoding process. The content-aware decoding process may be dynamic and determine connection structures of bits and content nodes based on patterns in data. In some cases, the decoder may connect non-adjacent bits to a content node based on a content-aware decoding process. In other cases, the decoder may connect a first number of bits to a first content node and a second number of bits to a second content node. In such cases, the first number of bits and the second number of bits are a different number.

Abstract: A method and apparatus for obtaining data from a memory, estimating a probability of data values of the obtained data based on at least one of a source log-likelihood ratio and a channel log-likelihood ratio, wherein each bit in the obtained data has an associated log-likelihood ratio, determining at least one data pattern parameter for the data and performing a decoding process using the at least one data pattern parameters to determine a decoded data set.

Abstract: A method and apparatus for obtaining data from a memory, estimating a probability of data values of the obtained data based on at least one of a source log-likelihood ratio and a channel log-likelihood ratio, wherein each bit in the obtained data has an associated log-likelihood ratio, determining at least one data pattern parameter for the data and performing a decoding process using the at least one data pattern parameters to determine a decoded data set.

Abstract: A device that includes a non-volatile memory and a controller. The controller is coupled to the non-volatile memory. The controller includes a non-transitory computer readable medium and a processor. The controller includes computer executable instructions stored in the computer readable medium to, using the processor, retrieve a flash memory page from the non-volatile memory, determine a memory parameter associated with the flash memory pages, determine a read threshold voltage scanning order based on the memory parameter, and perform read threshold voltage calibration according to the read threshold voltage scanning order.

Abstract: A method for punctured bit estimation includes receiving a punctured codeword. The method further includes generating a reconstructed codeword using the punctured codeword and at least one punctured bit having a default logic value. The method further includes generating a syndrome vector for the reconstructed codeword. The method further includes determining, using the syndrome vector, a number of unsatisfied parity-checks for the at least one punctured bit. The method further includes determining, for the at least one punctured bit, a bit value using, at least, the number of unsatisfied parity-checks associated with the at least one punctured bit.