Patents by Inventor David Briggs

David Briggs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210289072
    Abstract: Systems, apparatuses, and methods for enabling communication between parties are disclosed. A system may include a first communication device associated with a first user and a second communication device associated with a second user. The system may include a first communication channel between the first user and the second user for transmitting call data between the first communication device and the second communication device. The system may include a second communication channel between the first user and the second user established concurrently with the first communication channel. The second communication channel may be separate from the first communication channel. The second communication channel may be established by connection of the communication session participants to a multipoint control unit that is configured to transmit media data between the first communication device and the second communication device.
    Type: Application
    Filed: March 11, 2020
    Publication date: September 16, 2021
    Applicant: Sorenson IP Holdings, LLC
    Inventors: Daniel Baker, Jason Briggs, Steve Saunders, Amy Benich, Isaac Roach, Mark Grossinger, David Lance Pickett, Thomas Hawkes, Kevin Selman
  • Patent number: 11111260
    Abstract: A method for forming 1,3,5,7-tetraalkyl-6-(2,4-dimethoxyphenyl)-2,4,8-trioxa-6-phosphaadamantane includes obtaining a solution comprising an ethereal solvent and an aluminum hydride, adding dichloro(2,4-dimethoxyphenyl)phosphine to the solution to produce 2,4-dimethoxyphenylphosphine, and reacting the 2,4-dimethoxyphenylphosphine with an acidic mixture comprising diones to produce 1,3,5,7-tetraalkyl-6-(2,4-dimethoxyphenyl)-2,4,8-trioxa-6-phosphaadamantane. The solution has a temperature from IN greater than ?20 C. to 50 C. throughout the method. Another method for forming 1,3,5,7-tetraalkyl-6-(2,4-dimethoxyphenyl)-2,4,8-tri-oxa-6-phosphaadamantane includes obtaining dichloro(2,4-dimethoxyphenyl)phosphine, forming 2,4-dimethoxyphenylphosphine by adding the dichloro(2,4-dimethoxyphenyl)phosphine to a solution comprising at least one solvent and an aluminum hydride, reacting the 2,4-dimethoxyphenylphosphine with a mixture to produce 1,3,5,7-tetraalkyl-6-(2,4-dimethoxyphenyl)-2,4,8-trioxa-6-phosphaadamantane.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: September 7, 2021
    Assignee: Dow Global Technologies LLC
    Inventors: Jessica L. Klinkenberg, John R. Briggs, Andrew M. Camelio, Robert David Grigg, Siyu Tu
  • Patent number: 11113175
    Abstract: A system for discovering semantic relationships in computer programs is disclosed. In particular, the system may synergistically identify and validate semantic relationships, concepts, and groupings associated with data elements within a static or dynamic, time varying, source input. The system may utilize feature extractors to extract features from the input and reasoners to develop associations using data from multiple feature set types, and, can thus generate reliable, robust, and complete sets of semantic relationships from the input. The system may generate hypotheses associated with the relationships, concepts, and groupings, and validate the hypotheses by testing an application under evaluation by the system and observing the outputs generated from the testing.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: September 7, 2021
    Assignee: THE ULTIMATE SOFTWARE GROUP, INC.
    Inventors: David Adamo, John A. Maliani, Robert L. Vanderwall, Michael L. Mattera, Dionny Santiago, Brian R. Muras, Keith A. Briggs, Tariq King
  • Publication number: 20210227998
    Abstract: The invention features a refrigerator cabinet door frame. The frame includes a thermally conductive outer frame, a thermally insulating inner frame member, and a sealing plate. The outer frame member includes a forward end having an outer surface that is disposed outside of a refrigerated cabinet with the frame mounted, and a rearward end defining a joint. The inner frame member includes a first end retained in the joint, and a second end. The sealing plate includes a first edge coupled to the outer frame member at the rearward end, forward of the joint, a second edge supported by the second end of the inner frame member, and a thermally conductive sealing surface. The first edge of the sealing plate is coupled to the outer frame member such that the sealing surface and the outer surface of the outer frame member together form a continuous heat transfer path.
    Type: Application
    Filed: January 25, 2021
    Publication date: July 29, 2021
    Inventors: Paul J. Artwohl, Jeffery W. Nicholson, Matthew Rolek, David Briggs Baugh
  • Publication number: 20210210380
    Abstract: A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.
    Type: Application
    Filed: March 25, 2021
    Publication date: July 8, 2021
    Applicant: Tessera, Inc.
    Inventors: Benjamin David Briggs, Joe Lee, Theodorus Eduardus Standaert
  • Patent number: 11056429
    Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: July 6, 2021
    Assignee: Tessera, Inc.
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Publication number: 20210153042
    Abstract: A device initiates voice communication sessions with a media resource function processor (MRFP) of a network, where each voice communication session communicates audio data via one or more network devices of the network. For each voice communication session, the device sends first audio data to the MRFP and receives second audio data from the MRFP via the voice communication session, processes the first audio data and second audio data to determine one or more characteristics of the second audio data, and generates a record concerning the voice communication session based on the one or more characteristics of the second audio data. The device generates a report based on a respective record of each voice communication session, processes the report using an artificial intelligence technique to identify an issue concerning at least one network device, and performs, based on identifying the issue, an action concerning the at least one network device.
    Type: Application
    Filed: January 28, 2021
    Publication date: May 20, 2021
    Applicant: Verizon Patent and Licensing Inc.
    Inventor: Charles David BRIGGS
  • Patent number: 10985056
    Abstract: A method of forming fully aligned vias in a semiconductor device, the method including recessing a first level interconnect line below a first interlevel dielectric (ILD), laterally etching the exposed upper portion of the first interlevel dielectric bounding the recess, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 20, 2021
    Assignee: Tessera, Inc.
    Inventors: Benjamin David Briggs, Joe Lee, Theodorus Eduardus Standaert
  • Patent number: 10964588
    Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: March 30, 2021
    Assignee: Tessera, Inc.
    Inventors: Christopher J. Penny, Benjamin David Briggs, Huai Huang, Lawrence A. Clevenger, Michael Rizzolo, Hosadurga Shobha
  • Patent number: 10957584
    Abstract: A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: March 23, 2021
    Assignee: Tessera, Inc.
    Inventors: Benjamin David Briggs, Joe Lee, Theodorus Eduardus Standaert
  • Patent number: 10924946
    Abstract: A device initiates voice communication sessions with a media resource function processor (MRFP) of a network, where each voice communication session communicates audio data via one or more network devices of the network. For each voice communication session, the device sends first audio data to the MRFP and receives second audio data from the MRFP via the voice communication session, processes the first audio data and second audio data to determine one or more characteristics of the second audio data, and generates a record concerning the voice communication session based on the one or more characteristics of the second audio data. The device generates a report based on a respective record of each voice communication session, processes the report using an artificial intelligence technique to identify an issue concerning at least one network device, and performs, based on identifying the issue, an action concerning the at least one network device.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: February 16, 2021
    Assignee: Verizon Patent and Licensing Inc.
    Inventor: Charles David Briggs
  • Patent number: 10898011
    Abstract: The invention features a refrigerator cabinet door frame. The frame includes a thermally conductive outer frame, a thermally insulating inner frame member, and a sealing plate. The outer frame member includes a forward end having an outer surface that is disposed outside of a refrigerated cabinet with the frame mounted, and a rearward end defining a joint. The inner frame member includes a first end retained in the joint, and a second end. The sealing plate includes a first edge coupled to the outer frame member at the rearward end, forward of the joint, a second edge supported by the second end of the inner frame member, and a thermally conductive sealing surface. The first edge of the sealing plate is coupled to the outer frame member such that the sealing surface and the outer surface of the outer frame member together form a continuous heat transfer path.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: January 26, 2021
    Assignee: Anthony, Inc.
    Inventors: Paul J. Artwohl, Jeffery W. Nicholson, Matthew Rolek, David Briggs Baugh
  • Publication number: 20200388525
    Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
    Type: Application
    Filed: May 6, 2020
    Publication date: December 10, 2020
    Applicant: Tessera, Inc.
    Inventors: Christopher J. Penny, Benjamin David Briggs, Huai Huang, Lawrence A. Clevenger, Michael Rizzolo, Hosadurga Shobha
  • Publication number: 20200388568
    Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.
    Type: Application
    Filed: March 12, 2020
    Publication date: December 10, 2020
    Applicant: Tessera, Inc.
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Publication number: 20200313611
    Abstract: The present invention is directed to a covering for a clamping assembly used to connect and ground solar panel modules to a mounting rail. The covering comprises a sleeve including an outer cover for connecting to the solar panel module and a connector shaped to be contained within the outer cover and connected to the outer cover through two or more flanges. The connector has an opening there through to receive a female member of the clamping assembly.
    Type: Application
    Filed: June 15, 2020
    Publication date: October 1, 2020
    Applicant: IronRidge, Inc.
    Inventors: Jon Ash, David Briggs, Shawn Meine, Bryan Lester
  • Patent number: 10785590
    Abstract: A computer-implemented method for calibrating audio of a virtual reality device, the method comprising: determining a difference between a perceived tone location and an actual audible tone location, in response to an emitting of the actual audible tone; wherein the tone comprises a spectral tone, and creating and calibrating a user ear model by: emitting the spectral tone at a random time during a simulation by the virtual reality device; determining the perceived tone location during the simulation; and computing an error adjustment for one or more geometric variables of a default ear model based on a result of the determining.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Leigh Anne Hodges Clevenger, Christopher J. Penny, Michael Rizzolo, Aldis Gunars Sipolins
  • Patent number: 10770348
    Abstract: A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: September 8, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Michael Rizzolo
  • Publication number: 20200277862
    Abstract: A method and apparatus for minimizing engine weight for a turbine engine by utilizing one or more discrete protuberances disposed on an engine component wall. The wall can have a nominal thickness to decrease engine weight while the protuberances can provide increased discrete thicknesses for providing one or more cooling holes. The increased thickness at the protuberances provides for an increased thickness to provide sufficient length to increase cooling hole effectiveness.
    Type: Application
    Filed: May 8, 2020
    Publication date: September 3, 2020
    Inventors: Douglas Gerard Konitzer, Scott Ronald Bunker, Robert David Briggs
  • Patent number: 10752039
    Abstract: A document including a Directed Self-Assembly (DSA) pattern including a unique and randomized pattern embedded on the document, where the DSA is formed by using two different-length polymer chains.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Michael Rizzolo
  • Patent number: 10690055
    Abstract: Gas turbine engine components are provided which utilize an insert to provide cooling air along a cooled surface of an engine component. The insert provides cooling holes or apertures which face the cool side surface of the engine component and direct cooling air onto that cool side surface. The apertures may be formed in arrays and directed at an oblique or a non-orthogonal angle to the surface of the insert and may be at an angle to the surface of the engine component being cooled. An engine component assembly is provided with counterflow impingement cooling, comprising an engine component cooling surface having a cooling fluid flow path on one side and a second component adjacent to the first component. The second component may have a plurality of openings forming an array wherein the openings extend through the second component at a non-orthogonal angle to the surface of the second component.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: June 23, 2020
    Assignee: General Electric Company
    Inventors: Curtis Walton Stover, Jonathan Michael Rausch, Satoshi Atsuchi, Gulcharan Singh Brainch, Robert David Briggs, Ronald Scott Bunker, Ambarish Jayant Kulkarni, Michael Alan Meade, Byron Andrew Pritchard, Robert Proctor