Patents by Inventor David Briggs

David Briggs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10280785
    Abstract: A shroud assembly for a turbine section of a turbine engine includes a shroud plate in thermal communication with a hot combustion gas flow and a baffle overlying the shroud plate to define a region. One or more shaped cooling features are located along the region such that a cooling fluid flow passing through the region encounters the shaped cooling features to increase the turbulence of the cooling fluid flow.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: May 7, 2019
    Assignee: General Electric Company
    Inventors: Robert David Briggs, Gulcharan Singh Brainch, Curtis Walton Stover
  • Publication number: 20190106991
    Abstract: An engine component for a gas turbine engine includes a film-cooled substrate having a hot surface facing hot combustion gas flow and a cooling surface facing a cooling fluid flow. A film hole extends through the substrate to an outlet on the hot surface. A flow conditioning structure is provided upstream of the outlet.
    Type: Application
    Filed: October 16, 2018
    Publication date: April 11, 2019
    Inventors: Ronald Scott Bunker, Robert David Briggs
  • Patent number: 10214967
    Abstract: In this novel PDC cutter, diamond powders of different composition and/or different grain size, are distributed, shaped, and compacted with a novel pressing tool, in multiple stages, spatially arranged into different regions of the PDC diamond body, then HPHT sintered to form one PDC body with spatially varying hardness, toughness and thermal resistance.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: February 26, 2019
    Inventors: Samer Alkhalaileh, David Briggs, Jiang Xiaole, Zhao Yunliang
  • Patent number: 10174620
    Abstract: An airfoil comprises one or more internal cooling circuits. The cooling circuit can further comprise a near wall cooling mesh, fluidly coupling a supply passage to a mesh plenum. The mesh plenum can be disposed adjacent to the external surface of the airfoil having a plurality of film holes extending between the mesh plenum and the external surface of the airfoil. The mesh plenum can further comprise a cross-sectional area sized to facilitate machining of the film holes without damage to the interior of the airfoil.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: January 8, 2019
    Assignee: General Electric Company
    Inventors: Matthew Lee Krumanaker, Weston Nolan Dooley, Steven Robert Brassfield, David Benjamin Helmer, Jeremy Clyde Bailey, Robert David Briggs
  • Publication number: 20180366408
    Abstract: A method of forming a semiconductor device includes forming a porous dielectric layer including a recessed portion, forming a conductive layer in the recessed portion of the porous dielectric layer, and forming a conformal cap layer on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the conformal cap layer.
    Type: Application
    Filed: July 30, 2018
    Publication date: December 20, 2018
    Inventors: Benjamin David BRIGGS, Lawrence A. CLEVENGER, Bartlef H. DEPROSPO, Huai HUANG, Christopher J. PENNY, Michael RIZZOLO
  • Publication number: 20180354291
    Abstract: An anti-counterfeiting method, system, and non-transitory computer readable medium an anti-counterfeiting system, include a production circuit configured to produce a Directed Self-Assembly (DSA) pattern including a unique pattern, an analysis circuit configured to analyze the unique pattern, an embedding circuit configured to embed the unique pattern on a document, and a verification circuit configured to verify that the unique pattern embedded on the document corresponds to the document.
    Type: Application
    Filed: August 21, 2018
    Publication date: December 13, 2018
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Michael Rizzolo
  • Patent number: 10150323
    Abstract: An anti-counterfeiting method, system, and non-transitory computer readable medium, include a production circuit configured to produce a Directed Self-Assembly (DSA) pattern including a unique pattern, an analysis circuit configured to analyze the unique pattern, an embedding circuit configured to embed the unique pattern on a document, and a verification circuit configured to verify that the unique pattern embedded on the document corresponds to the document.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: December 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Michael Rizzolo
  • Publication number: 20180344054
    Abstract: The invention features a refrigerator cabinet door frame. The frame includes a thermally conductive outer frame, a thermally insulating inner frame member, and a sealing plate. The outer frame member includes a forward end having an outer surface that is disposed outside of a refrigerated cabinet with the frame mounted, and a rearward end defining a joint. The inner frame member includes a first end retained in the joint, and a second end. The sealing plate includes a first edge coupled to the outer frame member at the rearward end, forward of the joint, a second edge supported by the second end of the inner frame member, and a thermally conductive sealing surface. The first edge of the sealing plate is coupled to the outer frame member such that the sealing surface and the outer surface of the outer frame member together form a continuous heat transfer path.
    Type: Application
    Filed: August 8, 2018
    Publication date: December 6, 2018
    Inventors: Paul J. Artwohl, Jeffery W. Nicholson, Matthew Rolek, David Briggs Baugh
  • Patent number: 10134674
    Abstract: A method of fabricating a metallization layer of a semiconductor device in which copper is used for an interconnect material and cobalt is used to encapsulate the copper. A material is introduced that will interact with the cobalt to cause a hexagonal-close-packed (HCP) crystal structure of cobalt to change to a face-centered-cubic (FCC) crystal structure of cobalt, the FCC crystal structure providing a resistance of the cobalt to migrate.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, James J. Kelly, Koichi Motoyama, Roger Allan Quon, Michael Rizzolo, Theodorus Eduardus Standaert
  • Patent number: 10132166
    Abstract: An engine component for a gas turbine engine includes a film-cooled substrate having a hot surface facing hot combustion gas flow and a cooling surface facing a cooling fluid flow. A film hole extends through the substrate to an outlet on the hot surface. A flow conditioning structure is provided upstream of the outlet.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: November 20, 2018
    Assignee: General Electric Company
    Inventors: Ronald Scott Bunker, Robert David Briggs
  • Patent number: 10109579
    Abstract: A method of forming a semiconductor device, includes forming a conductive layer in a recessed portion of a porous dielectric layer, partially removing a top portion of the conductive layer while maintaining a height of the porous dielectric layer, forming a conformal cap layer on the porous dielectric layer and the conductive layer in the recessed portion, polishing the conformal cap layer to form a gap in the conformal cap layer, such that an upper surface of the porous dielectric layer is exposed through the gap and an upper surface of the conductive layer is protected by the cap layer, and performing a heat treatment to burn out a pore filler of the porous dielectric layer through the exposed upper surface of the porous dielectric layer.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Patent number: 10094714
    Abstract: A temperature measurement system includes at least one temperature measurement probe. The at least one temperature measurement probe includes at least one hollow filament configured to emit thermal radiation in a predetermined and substantially continuous wavelength band at least partially representative of a temperature of the at least one hollow filament. The at least one hollow filament has a first diameter and a first emissivity. The at least one temperature measurement probe also includes at least one thin filament extending within at least a portion of the at least one hollow filament. The at least one thin filament is configured to emit thermal radiation in a predetermined and substantially continuous wavelength band at least partially representative of a temperature of the at least one thin filament. The at least one thin filament has a second emissivity and a second diameter less than the first diameter.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: October 9, 2018
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Guanghua Wang, Bin Ma, James Peter DeLancey, K. M. K. Genghis Khan, Carlos Bonilla Gonzalez, Robert David Briggs, Nirm Velumylum Nirmalan
  • Publication number: 20180249271
    Abstract: A binaural audio calibration method, system, and computer program product for using behavioral data and sensor data to calibrate binaural audio to a specific user and creating a personalized binaural audio which can lead to greater immersion and allow user attention to be more effectively controlled.
    Type: Application
    Filed: February 27, 2017
    Publication date: August 30, 2018
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Leigh Anne Hodges Clevenger, Christopher J. Penny, Michael Rizzolo, Aldis Gunars Sipolins
  • Patent number: 10045638
    Abstract: The invention features a refrigerator cabinet door frame. The frame includes a thermally conductive outer frame, a thermally insulating inner frame member, and a sealing plate. The outer frame member includes a forward end having an outer surface that is disposed outside of a refrigerated cabinet with the frame mounted, and a rearward end defining a joint. The inner frame member includes a first end retained in the joint, and a second end. The sealing plate includes a first edge coupled to the outer frame member at the rearward end, forward of the joint, a second edge supported by the second end of the inner frame member, and a thermally conductive sealing surface. The first edge of the sealing plate is coupled to the outer frame member such that the sealing surface and the outer surface of the outer frame member together form a continuous heat transfer path.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: August 14, 2018
    Assignee: Anthony, Inc.
    Inventors: Paul J. Artwohl, Jeffery W. Nicholson, Matthew Rolek, David Briggs Baugh
  • Publication number: 20180190585
    Abstract: A method of forming a semiconductor device, includes forming a conductive layer in a recessed portion of a porous dielectric layer, partially removing a top portion of the conductive layer while maintaining a height of the porous dielectric layer, forming a conformal cap layer on the porous dielectric layer and the conductive layer in the recessed portion, polishing the conformal cap layer to form a gap in the conformal cap layer, such that an upper surface of the porous dielectric layer is exposed through the gap and an upper surface of the conductive layer is protected by the cap layer, and performing a heat treatment to burn out a pore filler of the porous dielectric layer through the exposed upper surface of the porous dielectric layer.
    Type: Application
    Filed: February 28, 2018
    Publication date: July 5, 2018
    Inventors: Benjamin David BRIGGS, Lawrence A. CLEVENGER, Bartlet H. DEPROSPO, Huai HUANG, Christopher J. PENNY, Michael RIZZOLO
  • Patent number: 9997451
    Abstract: A semiconductor device includes a porous dielectric layer formed on an interconnect layer and including a recessed portion, a conductive layer formed in the recessed portion, and a conformal cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the conformal cap layer. Porous dielectric material is protected by back-filled pore fillers or leave-in porogens from process integration such as chemical mechanical polishing (CMP). The pore fillers or porogens are removed after CMP and Cap process to achieve low capacitance. A self-aligned cap protects the conductor metal from exposing the severe conditions during the pore filler or porogen removal process.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Publication number: 20180146798
    Abstract: The invention features a refrigerator cabinet door frame. The frame includes a thermally conductive outer frame, a thermally insulating inner frame member, and a sealing plate. The outer frame member includes a forward end having an outer surface that is disposed outside of a refrigerated cabinet with the frame mounted, and a rearward end defining a joint. The inner frame member includes a first end retained in the joint, and a second end. The sealing plate includes a first edge coupled to the outer frame member at the rearward end, forward of the joint, a second edge supported by the second end of the inner frame member, and a thermally conductive sealing surface. The first edge of the sealing plate is coupled to the outer frame member such that the sealing surface and the outer surface of the outer frame member together form a continuous heat transfer path.
    Type: Application
    Filed: November 28, 2016
    Publication date: May 31, 2018
    Inventors: Paul J. Artwohl, Jeffery W. Nicholson, Matthew Rolek, David Briggs Baugh
  • Publication number: 20180122692
    Abstract: A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.
    Type: Application
    Filed: December 22, 2017
    Publication date: May 3, 2018
    Inventors: Benjamin David Briggs, Joe Lee, Theodorus Eduardus Standaert
  • Publication number: 20180122691
    Abstract: A method of forming fully aligned vias in a semiconductor device, the method including recessing a first level interconnect line below a first interlevel dielectric (ILD), laterally etching the exposed upper portion of the first interlevel dielectric bounding the recess, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.
    Type: Application
    Filed: December 22, 2017
    Publication date: May 3, 2018
    Inventors: Benjamin David Briggs, Joe Lee, Theodorus Eduardus Standaert
  • Publication number: 20180114723
    Abstract: A method of forming fully aligned vias in a semiconductor device includes forming an Mx level interconnect line embedded in an Mx interlevel dielectric (ILD). The Mx level interconnect is recessed below the Mx interlevel dielectric or a dielectric is selectively deposited on the Mx interlevel dielectric. The method also includes laterally etching the exposed upper portion of the Mx interlevel dielectric bounding the recess or laterally etching the selectively deposited dielectric. A dielectric cap layer and an Mx+1 level interlevel dielectric is deposited on top of the Mx interlevel dielectric, and a via opening is formed.
    Type: Application
    Filed: October 26, 2016
    Publication date: April 26, 2018
    Inventors: Benjamin David Briggs, Joe Lee, Theodorus Eduardus Standaert