Abstract: One aspect of the present disclosure relates to an electronic circuit including: a first clock net with a first clock wire coupled to a first set of latches or flip-flops; a second clock net with a second clock wire coupled to a second set of latches or flip-flops; a first driver circuit coupled to the first clock wire and configured to drive the first clock net to one of a first clock state or a second clock state; a second driver circuit coupled to the second clock wire and configured to drive the second clock net to one of the first clock state or the second clock state; and a shared device interconnecting the first and second clock nets, the shared device configured to couple the first clock wire to the second clock wire to transfer charge between the first clock net and the second clock net.

Abstract: The present disclosure generally relates to using built-in self-test (BIST) for on-chip error detection. In some aspects, a method includes receiving information about one or more parameters for a built-in self-test (BIST) operation, generating a nonce for each iteration of the BIST operation according to the one or more parameters, and computing a hash value for each iteration of the BIST operation using the nonce as an input to a cryptographic hash function. The method further includes transmitting, to multiple hash engines, information about the nonce and the hash value for each iteration of the BIST operation. The method further includes receiving, from each hash engine, a response with information indicating a number of correct results computed by that hash engine. The method further includes comparing the indicated number of correct results to an expected number of correct results for the BIST operation.

Abstract: An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.

Abstract: An integrated circuit (IC) chip receives an input signal on a bus connecting a number of IC chips in series. The IC chip is one of the number of IC chips. The IC chip performs a combining operation and an inverting operation on a signal produced by the IC chip and the input signal to generate an output signal. The IC chip sends the output signal to a next chip of the number of IC chips on the bus.

Abstract: An integrated circuit (IC) chip receives an input signal on a bus connecting a number of IC chips in series. The IC chip is one of the number of IC chips. The IC chip determines whether the bus is in a busy state or an idle state. If the IC chip determines that the bus is in the idle state, the IC chip blocks communication from upstream chips on the bus, and transmit data on the bus. If the IC chip determines that the bus is in the busy state, the IC chip delays transmitting the data on the bus for a delay period, and transmits its data on the bus if the bus is determined to be in the idle state upon expiry of the delay period.

Abstract: An ultraviolet-curable (UV-curable) adhesive composition is disclosed. The adhesive composition comprises: A) an epoxy curing agent component; B) a microencapsulated epoxy resin component; C) an expansion agent component; D) a binder component; and E) a photoinitiator component. The adhesive composition is useful for forming an adhesive. In various embodiments, the adhesive composition is in the form of a stick. The adhesive composition is useful for securing a fastener (e.g. in a borehole).

Abstract: An example system, includes clock synchronization circuitry, first data processing circuitry, and second data processing circuitry electrically coupled to the clock synchronization circuitry and the first processing circuitry. The clock synchronization circuitry is configured to receive a first signal, and output a second signal synchronized to a clock domain of the second data processing circuitry. The first data processing circuitry is configured to perform one or more first computations based on the first signal, and provide, to the second data processing circuitry, a result corresponding to the one or more first computations. The second data processing circuitry is configured to perform one or more second computations based on the second signal, determine whether the one or more second computations satisfies a selection criterion, and generate output data representing whether the one or more second computations satisfies the selection criterion.

Abstract: An integrated circuit (IC) chip receives an input signal on a bus connecting a number of IC chips in series. The IC chip is one of the number of IC chips. The IC chip performs a combining operation and an inverting operation on a signal produced by the IC chip and the input signal to generate an output signal. The IC chip sends the output signal to a next chip of the number of IC chips on the bus.

Abstract: The field of the invention relates to bicycle systems, especially to bicycle systems adapted for use with smartphones, to smartphones configured for use with bicycle systems, and to methods and to computer software for use with such bicycle systems or smartphones, and to servers configured to communicate with such bicycle systems or smartphones. According to a first aspect of the invention, there is provided a bicycle system including a bicycle, the bicycle system including a processor integral to the bicycle, the bicycle system further including a battery integral to the bicycle, wherein the processor is powerable by the battery, the bicycle system including a smartphone holder configurable to receive a smartphone and to connect the smartphone to the processor, wherein in use the smartphone holder is attachable to, and detachable from, the smartphone.

Abstract: An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.

Abstract: An electronic system for calculating and mining digital currency using circuits optimized for efficient utilization of hash engine circuitry by determining an effective hash clock operational frequency for one or more hash engines in the system. The hash engines can be evaluated to determine a maximum operational frequency for a given error threshold. The hash engines can also be partitioned into one or more hash engine groups to allow different groups to operate at different overclocked frequencies.

Abstract: The field of the invention relates to bicycle systems, especially to bicycle systems adapted for use with smartphones, to smartphones configured for use with bicycle systems, and to methods and to computer software for use with such bicycle systems or smartphones, and to servers configured to communicate with such bicycle systems or smartphones. According to a first aspect of the invention, there is provided a bicycle system including a bicycle, the bicycle system including a processor integral to the bicycle, the bicycle system further including a battery integral to the bicycle, wherein the processor is powerable by the battery, the bicycle system including a smartphone holder configurable to receive a smartphone and to connect the smartphone to the processor, wherein in use the smartphone holder is attachable to, and detachable from, the smartphone.

Abstract: An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.

Abstract: A mobile processing system is disclosed for the removal of radioactive contaminants from nuclear process wastewater. The system is fully scalable, modular, and portable allowing the system to be fully customizable according to site-specific remediation requirements. It is designed to be both transported and operated from standard sized intermodal containers or custom designed enclosures for increased mobility between sites and on-site, further increasing the speed and ease with which the system may be deployed. Additionally, the system is completely modular wherein the various modules perform different forms or stages of wastewater remediation and may be connected in parallel and/or in series. Depending on the needs of the site, one or more different processes may be used. In some embodiments, one or more of the same modules may be used in the same operation.

Abstract: Methods, circuits, apparatus, and systems for managing multi-phase clocking signals for integrated circuit devices are provided. In one aspect, an integrated circuit device includes: a clock signal generator configured to generate a reference clock signal and a plurality of processing units coupled to the clock signal generator. At least one of the plurality of processing units includes: a phase generator configured to selectively generate at least two sets of multi-phase clock signals based on the reference clock signal and corresponding control signals, the at least two sets of multi-phase clock signals having different respective frequencies; and a computation unit configured to perform at least one computing function based on a selected one of the at least two sets of multi-phase clock signals.

Abstract: A mobile processing system is disclosed for the removal of radioactive contaminants from nuclear process wastewater. The system is fully scalable, modular, and portable allowing the system to be fully customizable according to site-specific remediation requirements. It is designed to be both transported and operated from standard sized intermodal containers or custom designed enclosures for increased mobility between sites and on-site, further increasing the speed and ease with which the system may be deployed. Additionally, the system is completely modular wherein the various modules perform different forms or stages of wastewater remediation and may be connected in parallel and/or in series. Depending on the needs of the site, one or more different processes may be used. In some embodiments, one or more of the same modules may be used in the same operation.

Abstract: In an example method, a system accesses sensor data representing a temperature of one or more computer chips of a computer system configured to perform a cryptographic operation, and determines that the temperature has exceeded a threshold temperature. In response, the system dynamically adjusts a target computing performance of the one or more computer chips. Dynamically adjusting the target computing performance includes decreasing the target computing performance of the one or more computer chips by a first level; subsequent to decreasing the target computing performance of the one or more computer chips by the first level, determining that the temperature is less than the threshold temperature; and responsive to determining that the temperature is less than the threshold temperature, incrementally increasing the target computing performance of the one or more computer chips by a second level, where the first level is greater than the second level.

Abstract: Dynamically calculating an optimal operational efficiency configuration of a plurality of digital currency mining systems based on trending information related to the digital currency and extrinsic factors affecting the plurality of digital currency mining. The plurality of digital currency mining systems are sent configuration settings to achieve the optimal operational efficiency configuration.

Abstract: In an example method, a system accesses sensor data representing a temperature of one or more computer chips of a computer system configured to perform a cryptographic operation, and determines that the temperature has exceeded a threshold temperature. In response, the system dynamically adjusts a target computing performance of the one or more computer chips. Dynamically adjusting the target computing performance includes decreasing the target computing performance of the one or more computer chips by a first level; subsequent to decreasing the target computing performance of the one or more computer chips by the first level, determining that the temperature is less than the threshold temperature; and responsive to determining that the temperature is less than the threshold temperature, incrementally increasing the target computing performance of the one or more computer chips by a second level, where the first level is greater than the second level.

Abstract: Systems and methods of selecting a collection of compatible issue-ready instructions for parallel execution by functional units in a superscalar processor in a single clock cycle. All possible instructions (opcodes) to be executed by the functional units are pre-arranged into several scenarios based on potential resource conflicts among the instructions. Each scenario includes multiple groups of predefined instructions. During operation, concurrently for all the groups, an issue-ready instruction is identified with reference to each group based on group-specific selection policies. Further, based on the identified instructions, predefined policies are applied to select one or more scenarios and select among the picks of the selected scenarios. As a result, the output instructions of the selected scenarios are issued for parallel execution by the functional units.