Abstract: A pressure relief assembly includes a housing defining an air passage chamber having at least one opening, and a membrane flap secured within the air passage chamber. The membrane flap is configured to move into an open position to expose the opening(s) to relieve air pressure. A plurality of flap-retaining clips securely couple the membrane flap to the housing. Each of the plurality of the flap-retaining clips includes a main body. A housing-connecting tab extends from a first end of the main body. The housing-connecting tab is retained within a retaining channel formed in the housing. Opposed flap-retention wings laterally extend from opposite sides of the main body. A portion of the membrane flap is trapped between the opposed flap-retention wings and the housing to securely couple the membrane flap to the housing.

Abstract: The present invention relates to a method for controlling an internal combustion engine arrangement (100). The internal combustion engine arrangement (100) comprises a combustion cylinder (102) and an inlet valve (106) arranged to be positioned in a closed position at a distance before a piston (104) reaches a bottom dead center during normal operation. The inlet valve is further controllable to be arranged in the open position until the piston reaches the bottom dead center if a required volumetric efficiency of the combustion cylinder is higher than a volumetric efficiency during normal operation.

Abstract: The invention relates to a system (100) for operating a valve of an internal combustion engine (10), said system comprising a primary fluid circuit (60) configured to define a fluid passageway for circulating a compressible fluid medium there through being operatively connectable to an actuator (92) of an actuated flow control valve (90, 95) of said internal combustion engine, thereby capable of delivering a valve opening force.

Abstract: A method of implementing a processor architecture and corresponding system includes operands of a first size and a datapath of a second size. The second size is different from the first size. Given a first array of registers and a second array of registers, each register of the first and second arrays being of the second size, selecting a first register and corresponding second register from the first array and the second array, respectively, to perform operations of the first size. Advantageously, this allows a user, who is interfacing with the hardware processor through software, to provide data to the processor agnostic to the size of the registers and datapath bit-width of the processor.

Abstract: According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.

Abstract: An example embodiment combines use of a branch predictor with cache-like storage of previously executed branch targets to improve processor performance while minimizing hardware cost. The branch predictor is configured to predict both conditional branch and indirect branch targets and includes a combined predictor table configured to store at least one tagged conditional branch prediction in combination with at least one tagged indirect branch target prediction. The at least one tagged indirect branch target prediction is configured to include a predicted partial target address of a complete target address, the complete target address associated with an indirect branch instruction of a processor. The predictor includes prediction logic configured to use the predicted partial target address to produce a predicted complete target address of the complete target address for use by the processor prior to execution of the indirect branch instruction.

Abstract: An ALU is capable of generating a multiply accumulation by compressing like-magnitude partial products. Given N pairs of multiplier and multiplicand, Booth encoding is used to encode the multipliers into M digits, and M partial products are produced for each pair of with each partial product in a smaller precision than a final product. The partial products resulting from the same encoded multiplier digit position, are summed across all the multiplies to produce a summed partial product. In this manner, the partial product summation operations can be advantageously performed in the smaller precision. The M summed partial products are then summed together with an aggregated fixup vector for sign extension. If the N multipliers equal to a constant, a preliminary fixup vector can be generated based on a predetermined value with adjustment on particular bits, where the predetermined value is determined by the signs of the encoded multiplier digits.

Abstract: An instruction execution circuit operable to reduce two or more micro-operations into one by producing multiple permutation and merge results in one execution cycle. The execution circuit includes a permutation and merge switching fabric and a bank of multiplexers. For a fetched instruction, a decoder decodes an opcode to generate a set of control indications used to control the multiplexers to select bytes from the respective inputs that are destined for each of the multiple results. In this manner, multiple permutation results can be output from the execution circuits in one micro-operation.

Abstract: According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.

Abstract: Embodiments of tuning fork-based sensors are disclosed. The sensors may include a measurement sensor that includes a diaphragm disposed on a proximal end and a plurality of forks extending from the diaphragm toward the distal end of the sensor. The diaphragm may have a domed geometry defining a curved surface. The plurality of forks may extending from the curved surface of the diaphragm toward the distal end and each of the plurality of forks may include a stub portion connected to the diaphragm, a stem portion, and a paddle portion. Some sensors, such as measurement sensors, may include a stem portion formed from a corrosive material. A reference sensor may be provided to compensate for changes in frequency measurements due to temperature, viscosity, or other environmental factors present in the environment where the sensors are deployed.

Abstract: A mobile processing system is disclosed for the removal of radioactive contaminants from nuclear process waste water. The system is fully scalable, modular, and portable allowing the system to be fully customizable according the site-specific remediation requirements. It is designed to be both transported and operated from standard sized intermodal containers or custom designed enclosures for increased mobility between sites and on-site, further increasing the speed and ease with which the system may be deployed. Additionally, the system is completely modular wherein the various different modules perform different forms or stages of waste water remediation and may be connected in parallel and/or in series. Depending on the needs of the particular site, one or more different processes may be used. In some embodiments, one or more of the same modules may be used in the same operation.

Abstract: An ALU capable of generating a multiply accumulation by compressing like-magnitude partial products. Given N pairs of multiplier and multiplicand, Booth encoding is used to encode the multipliers into M digits, and M partial products are produced for each pair of with each partial product in a smaller precision than a final product. The partial products resulting from the same encoded multiplier digit position, are summed across all the multiplies to produce a summed partial product. In this manner, the partial product summation operations can be advantageously performed in the smaller precision. The M summed partial products are then summed together with an aggregated fixup vector for sign extension. If the N multipliers are equal to a constant, a preliminary fixup vector can be generated based on a predetermined value with adjustment on particular bits, where the predetermined value is determined by the signs of the encoded multiplier digits.

Abstract: A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.

Abstract: A system for preparing a bone for receiving an implant is described. The system includes a cutting tool and a cutting guide. The cutting tool includes a cut guard configured to sheath at least a portion of a cutting surface of the cutting tool, and an engagement portion. The cutting guide includes a baseplate configured to be positioned onto the bone and a cut guide portion removably attached to the baseplate. The cut guide portion includes a cutting channel, the cutting channel being sized and shaped to receive the engagement portion of the cut guard and guide the cutting tool to cut a receiving channel into the bone, wherein the receiving channel includes a depth profile matching an implant to be inserted into the receiving channel.

Abstract: A first memory request including a first virtual address is received. An entry in memory is accessed. The entry is selected using information associated with the first memory request, and includes at least a portion of a second virtual address (first data) and at least a portion of a third virtual address (second data). The difference between the first data and the second data is compared with differences between a corresponding portion of the first virtual address and the first data and the second data respectively. When a result of the comparison is true, then a fourth virtual address is determined by adding the difference between the first data and the second data to the first virtual address, and then data at the fourth virtual address is prefetched into the cache.

Abstract: A data structure (e.g., a table) stores a listing of prefetches. Each entry in the data structure includes a respective virtual address and a respective prefetch stride for a corresponding prefetch. If the virtual address of a memory request (e.g., a request to load or fetch data) matches an entry in the data structure, then the value of a counter associated with that entry is incremented. If the value of the counter satisfies a threshold, then the lookahead amount associated with the memory request is increased.

Abstract: A panel structure and a method of forming the panel structure are disclosed. The panel structure typically includes at least one panel associated with a material. The panel structure has been found particularly advantageous for use as an interior panel of an airplane.

Abstract: A pressure relief assembly (100) is configured to be secured to a portion of a vehicle. The pressure relief assembly (100) includes a pressure relief device (102) and a liquid-diverting cover (104) including at least one liquid diversion vane (150) that defines at least one air outlet (152). The liquid diversion vane(s) (150) is configured to block liquid from passing into an interior cabin of the vehicle. The air outlet(s) (152) allows airflow from within the vehicle to pass out of the interior cabin of the vehicle.

Abstract: An ALU capable of generating a multiply accumulation by compressing like-magnitude partial products. Given N pairs of multiplier and multiplicand, Booth encoding is used to encode the multipliers into M digits, and M partial products are produced for each pair of with each partial product in a smaller precision than a final product. The partial products resulting from the same encoded multiplier digit position, are summed across all the multiplies to produce a summed partial product. In this manner, the partial product summation operations can be advantageously performed in the smaller precision. The M summed partial products are then summed together with an aggregated fixup vector for sign extension. If the N multipliers equal to a constant, a preliminary fixup vector can be generated based on a predetermined value with adjustment on particular bits, where the predetermined value is determined by the signs of the encoded multiplier digits.

Abstract: A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.