Reset ramp control
A reset ramp control structure and method is described. A fast ramp down condition of a monitored voltage is detected and used to force the state of system reset. Delay between fast ramp detection and the forcing of system reset is adjustable. Operation is adaptable to include all DC power systems. The reset ramp control structure provides operational protection during fast ramp down conditions when standard reset circuitry may not be operational.
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This application claims priority from the provisional U.S. patent application titled “Reset Ramp Control”, filed Dec. 18, 2003 and identified by application Ser. No. 60/530,727, which is hereby incorporated herein by reference.
BACKGROUNDReset circuits are used to monitor power supplies in microprocessors, digital equipment, and various other electronic equipment and systems. A reset circuit is used to assert a reset signal whenever the supply voltage falls below a determined threshold voltage and to de-assert said reset signal when the supply voltage rises above a threshold. This reset signal may be input to the microprocessor, for example, to start the microprocessor in a known state during power up to prevent code execution errors, during power down to initiate a clean shutdown sequence, and during brownout to achieve control over marginal voltage conditions.
One deficiency of reset circuits is that proper assertion of reset signals during power down conditions may not reliably occur. The power supply voltage may decrease so quickly that existing reset detection circuitry may cease functioning before outputting a valid (changed) reset state.
The features of the invention believed to be novel are set forth with particularity in the appended claims. The invention itself however, both as to organization and method of operation, together with objects and advantages thereof, may be best understood by reference to the following detailed description of the invention, which describes certain exemplary embodiments of the invention, taken in conjunction with the accompanying drawings in which:
A structure and method for providing reset ramp control during fast ramp down conditions is presented, in accordance with certain embodiments of the present invention.
Many variations, equivalents and permutations of these illustrative exemplary embodiments of the invention will occur to those skilled in the art upon consideration of the description that follows. The particular examples utilized should not be considered to define the scope of the invention. For example discrete circuitry implementations and integrated circuit implementations, and hybrid approaches thereof, may be formulated using techniques of the present invention. Another example would be an implementation of the reset ramp control functional elements across a system.
While this invention is susceptible of embodiment in many different forms, there is shown in the drawings and will herein be described in detail specific embodiments, with the understanding that the present disclosure is to be considered as an example of the principles of the invention and not intended to limit the invention to the specific embodiments shown and described. In the description below, like reference numerals may be used to describe the same, similar or corresponding parts in the several views of the drawings.
For purposes of this document, the exact mechanical and electrical parameters of equipments are unimportant to an understanding of the invention, and many different types of electrical and mechanical components may be utilized without departing from the spirit and scope of the invention. An example is that components utilized in the circuit may differ as to value, power rating, and physical size. This document uses generalized descriptions by way of example only. Many variations for these constituent items are possible without departing from the spirit and scope of the invention.
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During power down of Vcc 105, the operation of bandgap reference 120 and comparator 125 become uncertain since active circuits have minimum operational voltage supply levels below which proper operation is not guaranteed and operation may become erratic and unpredictable. If during a fast ramp down of Vcc 105 operational voltage is not maintained such that a valid reset signal can be produced, the system will not be forced to a reset condition with the result that shutdown performance is unpredictable.
This is a problem that is addressed and solved by the present invention. During fast ramp downs of Vcc 105 the analog circuitry can stop working before it has a chance to respond to the fact that Vcc 105 has crossed the reset threshold. For example, if Vcc 105 drops from 5 VDC to 1 VDC in 100 ns or less, the bandgap and comparator can stop working before they respond to the crossing of the reset threshold and the reset output can be left in the wrong state.
Note that any reset system structure may be used to replace the example of
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When a Vcc 105 falling edge of sufficient magnitude occurs, the output of inverter 415 will change states from low to high. This will cause transistor 420 to go from an open state to a shorted state. In the open state, transistor 420 has a very high resistance between drain and source. In the shorted state, transistor 420 has a low resistance between drain and source. The voltage across capacitor 425 will therefore decay toward zero with a time constant determined primarily by the value of capacitor 425 and the shorted state resistance of transistor 420. Comparator 125 has a high output resistance as compared to the shorted state resistance of transistor 420, and therefore does not affect the time constant significantly. Other operational equivalent circuits are possible, of course. One example is if comparator 125 does not have high output resistance when not asserting reset, wherein the time constant calculation would take an interacting resistance into account using techniques known in the art.
Comparator 125 is the primary means for controlling the state of reset, which is reset output 430. If however a very fast drop in Vcc occurs, comparator 130 may not have time to respond. In that event the circuit of the present invention will provide reset functionality. When comparator 125 forces a reset to occur, as when Vcc 105 falls at a nominal or slow rate, it does so with a time constant determined by the value of capacitor 425 and the output resistance of the comparator, wherein the resistance is relatively low as the comparator is trying to force a low state at reset output 430. Transistor 420 is in the open state and provides a high resistance between drain and source, thus not significantly affecting the time constant. A time constant is desirable so that the reset output 430 will not change state as a result of fast temporary drops of Vcc 105 (glitches).
The circuit described above allows for reset output 430 to be in the correct state, even for fast ramp down and even if the bandgap or comparator are not working. In addition the circuit described above will force the reset to the correct state after a delay (time constant) which primarily depends on the value of capacitor 425 and the resistance of transistor 420 in the shorted state. Note that transistor 420 may be chosen to satisfy a time delay requirement.
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In the example circuit built and tested to verify operation of the present invention, the modified circuit of
Those of ordinary skill in the art will appreciate that many other circuit and system configurations can be readily devised to accomplish the desired end without departing from the spirit of the present invention.
While the invention has been described in conjunction with specific embodiments, it is evident that many alternatives, modifications, permutations and variations will become apparent to those of ordinary skill in the art in light of the foregoing description. By way of example, other types of devices and circuits may be utilized for any component or circuit as long as they provide the requisite functionality. A further example is that the described structure may be implemented as part of an integrated circuit, or a hybrid circuit, or a discrete circuit, or combinations thereof. Yet another example is that the features of the present invention may be adapted to all DC power systems regardless of voltages. Accordingly, it is intended that the present invention embrace all such alternatives, modifications and variations as fall within the scope of the appended claims.
Claims
1. A reset ramp control structure, comprising:
- a reset system element, coupled to the voltage to be monitored; and
- a fast ramp down detection element, which is coupled to the reset system element, and
- wherein during a ramp down condition of the voltage to be monitored the fast ramp down detection element forces an output of the reset system element to a known value and wherein during a slow ramp down condition of the voltage to be monitored the output of the reset system element is not forced by the fast ramp down detection element, and
- wherein the fast ramp down detection element further comprises: the voltage to be monitored is coupled to an anode of a diode; a first resistive element is coupled between a cathode of the diode and ground, and to an input terminal of an inverter; a gate of a transistor is coupled to an output of the inverter; a source of the transistor is coupled to ground; and a drain of the transistor is coupled to an output of the reset system element and to a capacitor.
2. The reset ramp control structure of claim 1, wherein a delay to force the output of the reset system element to the known value is set by modifying limits in the fast ramp down detection element.
3. The reset ramp control structure of claim 1, wherein the diode is a forward biased diode and the voltage drop of the forward biased diode is utilized to increase the sensitivity of the fast ramp down detection element.
4. The reset ramp control structure of claim 1, wherein the transistor of the fast ramp down detection element is utilized to initiate a delay in the output of the reset system.
5. The reset ramp control structure of claim 4, wherein resistance of the transistor of the fast ramp down detection element controls the magnitude of the delay.
6. The reset ramp control structure of claim 1, wherein a resistor of the fast ramp down detection element and a transistor of the fast ramp down detection element are utilized to initiate a delay in the output of the reset system.
7. The reset ramp control structure of claim 6, wherein the resistor substantially controls the magnitude of the delay.
8. The reset ramp control structure of claim 6, wherein the resistor and transistor are coupled in series.
9. A reset ramp control structure, comprising:
- a reset system element, coupled to the voltage to be monitored; and
- a fast ramp down detection element, which is coupled to the reset system element, and
- wherein during a ramp down condition of the voltage to be monitored the fast ramp down detection element forces an output of the reset system element to a known value and wherein during a slow ramp down condition of the voltage to be monitored the output of the reset system element is not forced by the fast ramp down detection element, wherein the fast ramp down detection element further comprises: the voltage to be monitored is coupled to a first conduction terminal of a first transistor; and a terminal of a first resistive element is coupled to a second conduction terminal of the first transistor and to an input terminal of an inverter, a control terminal of the first transistor coupled in a way to make the first transistor behave as a diode; and a gate of a second transistor is coupled to an output of the inverter; and the source of the second transistor is coupled to ground; and the drain of the second transistor is coupled to an output of the reset system element and to a capacitor.
10. The reset ramp control structure of claim 9, wherein the first and second transistors of a plurality of transistors of the fast ramp down detection element are utilized to initiate a delay in the output of the reset system.
11. The reset ramp control structure of claim 10, wherein the plurality of transistors are coupled in series.
12. The reset ramp control structure of claim 10, wherein the resistance of the plurality of transistors controls the magnitude of the delay.
13. The reset ramp control structure of claim 9, wherein a delay to force the output of the reset system element to the known value is set by modifying limits in the fast ramp down detection element.
14. A reset ramp control apparatus, operable to supply nonambiguous control of a system reset during fast ramp down conditions, comprising:
- a fast ramp down detection element to force an output of the system reset to a known state during a fast ramp down condition of a monitored voltage in accordance with a reset delay; and
- means to modify the reset delay,
- wherein during a slow ramp down condition of the voltage to be monitored the output of the system reset is not forced,
- wherein the fast ramp down detection element further comprises: the voltage to be monitored is coupled to an anode of a diode; a first resistive element is coupled between a cathode of the diode and ground, and to an input terminal of an inverter; a gate of a transistor is coupled to an output of the inverter; a source of the transistor is coupled to ground; and a drain of the transistor is coupled to an output of a reset element and to a capacitor.
15. The reset ramp control apparatus of claim 14, wherein a delay to force the output of the system reset to the known state is set by modifying limits in the reset ramp control apparatus.
16. The reset ramp control apparatus of claim 14, wherein the voltage drop of a forward biased diode of the fast ramp down detection element is utilized to increase the sensitivity of the reset ramp control apparatus.
17. The reset ramp control apparatus of claim 14, wherein a transistor of the fast ramp down detection element is utilized to initiate a delay in the output of the system reset.
18. The reset ramp control apparatus of claim 17, wherein resistance of the transistor of the fast ramp down detection element controls the magnitude of the delay.
19. The reset ramp control apparatus of claim 14, wherein a resistor and a transistor of the fast ramp down detection element are utilized to initiate a delay in the output of the system reset.
20. The reset ramp control structure of claim 19, wherein the resistor of the fast ramp down detection element substantially controls the magnitude of the delay.
21. The reset ramp control structure of claim 19, wherein the resistor and transistor of the fast ramp down detection element are coupled in series.
22. A reset ramp control apparatus, operable to supply nonambigiuous control of a system reset during fast ramp down conditions, comprising:
- a fast ramp down detection element to force an output of the system reset to a known state during a fast ramp down condition of a monitored voltage in accordance with a reset delay; and
- means to modify the reset delay, wherein during a slow ramp down condition of the voltage to be monitored the output of the system reset is not forced, wherein the fast ramp down detection element further comprises:
- the voltage to be monitored is coupled to a source of a first transistor; and
- a first resistive element is coupled between a drain a gate of the first transistor and ground, and to an input terminal of an inverter; and
- a gate of a second transistor is coupled to an output of the inverter; and
- a source of the second transistor is coupled to ground; and
- a drain of the second transistor is coupled to an output of the reset system element and to a capacitor.
23. The reset ramp control apparatus of claim 22, wherein a delay to force the output of the system reset to the known state is set by modifying limits in the reset ramp control apparatus.
24. The reset ramp control apparatus of claim 22, wherein the first and second transistors of a plurality of transistors of the fast ramp down detection element are utilized to initiate a delay in the output of the reset system.
25. The reset ramp control structure of claim 24, wherein the plurality of transistors of the fast ramp down detection element are coupled in series.
26. The reset ramp control structure of claim 24, wherein the resistance of the plurality of transistors of the fast ramp down detection element controls the magnitude of the delay.
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Type: Grant
Filed: Dec 15, 2004
Date of Patent: Aug 12, 2008
Patent Publication Number: 20050134346
Assignee: STMicroelectronics, Inc. (Carrollton, TX)
Inventors: David Charles McClure (Carrollton, TX), Rong Yin (Coppell, TX)
Primary Examiner: N. Drew Richards
Assistant Examiner: Thomas J Hiltunen
Attorney: Lisa K. Jorgenson
Application Number: 11/012,693
International Classification: H03K 17/22 (20060101);
