Abstract: A tester for testing a transformer is provided. The tester comprises a primary voltmeter and a plurality of secondary voltmeters. The tester may also comprise an ammeter in series with a voltage source configured to apply voltage to the transformer. The primary voltmeter is configured to measure voltage induced across a primary winding of the transformer, while the secondary voltmeters may simultaneously measure voltage outputs at secondary windings of the transformer. The tester is configured to calculate ratios, saturation curves, and knee points for multiple winding combinations based on the measurements simultaneously obtained by the ammeter and the primary and secondary voltmeters.

Abstract: A tester for testing a transformer is provided. The tester comprises a primary voltmeter and a plurality of secondary voltmeters. The tester may also comprise an ammeter in series with a voltage source configured to apply voltage to the transformer. The primary voltmeter is configured to measure voltage induced across a primary winding of the transformer, while the secondary voltmeters may simultaneously measure voltage outputs at secondary windings of the transformer. The tester is configured to calculate ratios, saturation curves, and knee points for multiple winding combinations based on the measurements simultaneously obtained by the ammeter and the primary and secondary voltmeters.

Abstract: A tester for testing a transformer is provided. The tester comprises a primary voltmeter and a plurality of secondary voltmeters. The tester may also comprise an ammeter in series with a voltage source configured to apply voltage to the transformer. The primary voltmeter is configured to measure voltage induced across a primary winding of the transformer, while the secondary voltmeters may simultaneously measure voltage outputs at secondary windings of the transformer. The tester is configured to calculate ratios, saturation curves, and knee points for multiple winding combinations based on the measurements simultaneously obtained by the ammeter and the primary and secondary voltmeters.

Abstract: A tester for testing a transformer is provided. The tester comprises a primary voltmeter and a plurality of secondary voltmeters. The tester may also comprise an ammeter in series with a voltage source configured to apply voltage to the transformer. The primary voltmeter is configured to measure voltage induced across a primary winding of the transformer, while the secondary voltmeters may simultaneously measure voltage outputs at secondary windings of the transformer. The tester is configured to calculate ratios, saturation curves, and knee points for multiple winding combinations based on the measurements simultaneously obtained by the ammeter and the primary and secondary voltmeters.

Abstract: A tester for testing a transformer is provided. The tester comprises a primary voltmeter and a plurality of secondary voltmeters. The tester may also comprise an ammeter in series with a voltage source configured to apply voltage to the transformer. The primary voltmeter is configured to measure voltage induced across a primary winding of the transformer, while the secondary voltmeters may simultaneously measure voltage outputs at secondary windings of the transformer. The tester is configured to calculate ratios, saturation curves, and knee points for multiple winding combinations based on the measurements simultaneously obtained by the ammeter and the primary and secondary voltmeters.

Abstract: A tester for testing a transformer is provided. The tester comprises a primary voltmeter and a plurality of secondary voltmeters. The tester may also comprise an ammeter in series with a voltage source configured to apply voltage to the transformer. The primary voltmeter is configured to measure voltage induced across a primary winding of the transformer, while the secondary voltmeters may simultaneously measure voltage outputs at secondary windings of the transformer. The tester is configured to calculate ratios, saturation curves, and knee points for multiple winding combinations based on the measurements simultaneously obtained by the ammeter and the primary and secondary voltmeters.

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire.

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact. The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via having a bonded connection with the substrate contact, a first contact on the wire proximate to the first side, and a second contact on the wire proximate to the second side. The through wire interconnect (TWI) also includes a polymer layer which partially encapsulates the through wire interconnect (TWI) while leaving the first contact exposed. The semiconductor component can be used to fabricate stacked-systems, module systems and test systems. A method for fabricating the semiconductor component can include a film assisted molding process for forming the polymer layer.

Abstract: Methods and apparatuses for releasably attaching support members to microfeature workpieces to support members are disclosed herein. In one embodiment, for example, a method for processing a microfeature workpiece including a plurality of microelectronic dies comprises forming discrete blocks of material at a first side of a support member. The blocks are arranged on the support member in a predetermined pattern. The method also includes depositing an adhesive material into gaps between the individual blocks of material and placing a first side of the workpiece in contact with the adhesive material and/or the blocks. The method further includes cutting through a second side of the workpiece to singulate the dies and to expose at least a portion of the adhesive material in the gaps. The method then includes removing at least approximately all the adhesive material from the support member and/or the workpiece with a solvent.

Abstract: A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact.

Abstract: A contactor card assembly for use with a semiconductor substrate. An upper keeper plate and a lower keeper plate each include a number of conductive pins extending therethrough, situated in vias filled with an elastomeric material and extending beyond the keeper plates to contact a substrate for testing. An intermediate keeper plate is situated between the upper and lower keeper plates and includes conductive pivot bars in channels filled with elastomeric material. Each conductive pin contacts a pivot bar on one side thereof to electrically communicate with a corresponding pin on the opposite side. Under compression, variations in the height of contacts on the substrate under test are adjusted for by the movement of the pins and pivoting of the pivot bar in the elastomeric material. Methods and process for creating the keeper plates and semiconductor and testing assemblies are also included in the present invention.

Abstract: A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact.

Abstract: A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact.

Abstract: A programmed material consolidation apparatus includes at least one fabrication site and a material consolidation system associated with the at least one fabrication site. The at least one fabrication site may be configured to receive one or more fabrication substrates, such as semiconductor substrates. A machine vision system with a translatable or locationally fixed camera may be associated with the at least one fabrication site and the material consolidation system. A cleaning component may also be associated with the at least one fabrication site. The cleaning component may share one or more elements with the at least one fabrication site, or may be separate therefrom. The programmed material consolidation apparatus may also include a substrate handling system, which places fabrication substrates at appropriate locations of the programmed material consolidation apparatus.

Abstract: Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.

Abstract: Methods for supporting substrates during programmed material consolidation include securing a substrate in position over a support with a surface and, optionally, other features that receive the at least one substrate and prevent unconsolidated material from contacting undesired regions, such as the bottom surface, of the at least one substrate.