Abstract: A drying apparatus for temporary location within a damp or waterlogged room is disclosed. The apparatus includes sensors to sense the level of temperature and humidity within the room, a heater to provide heat for the room, an air circulation fan for selectively circulating heated air within the room or selectively exhausting warm and humid air from the room and for allowing outside ambient air into the room. The apparatus being adapted to cyclically continue until the sensed humidity reaches a required level, the apparatus thereafter indicating, directly or indirectly, the completion of the drying process. A method of drying a room using such apparatus is also disclosed which employs a technique whereby the rate of change of the temperature increase is used to determine when humid air should be exhausted from the room. A time limit can also be use to determine when said exhausting takes place.

Abstract: An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terrace at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a pair of stepped terraces that approximately mirror the stepped terrace of the chip package and which provide vertical position references for an assembly tool that positions the set of semiconductor dies in the vertical stack during assembly of the chip package.

Abstract: Systems, methods, apparatus, and computer program products are provided for managing access of mobile stations to a plurality of wireless carriers. For example, in one embodiment, a central system can provide configuration files to mobile stations. The mobile stations can use the configuration files to access a plurality of different wireless carriers, with the different wireless carriers potentially implementing distinct technologies and communication standards and protocols.

Abstract: A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are adjacent to each other on the same side of a substrate in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. In addition, an input/output (I/O) integrated circuit is coupled to the optical integrated circuit between the substrate and the optical integrated circuit. This I/O integrated circuit includes high-speed I/O circuits and energy-efficient driver and receiver circuits and communicates with optical devices on the optical integrated circuit. By integrating the optical integrated circuit, the integrated circuit and the I/O integrated circuit in close proximity, the chip package may facilitate improved performance compared to chip packages with electrical interconnects.

Abstract: A multiple access Proximity Communication system in which electrical elements on an integrated circuit chip provide the multiplexing of multiple signals to a single electrical receiving element on another chip. Multiple pads formed on one chip and receiving separate signals may be capacitively coupled to one large pad on the other chip. Multiple inductive coils on one chip may be magnetically coupled to one large coil on another chip or inductive coils on three or more chips may be used for either transmitting or receiving. The multiplexing may be based on time, frequency, or code.

Abstract: A method of accessing rows and columns stored in a memory system that include memory chips that can be individually addressed and accessed is described. In order to leverage this capability, prior to performing a row-write request on the memory system, a computer system may transform the rows and the columns in a matrix. In particular, in response to receiving a row-write request to write to a row N in the matrix, the computer system rotates the row right by N elements, and writes the row in parallel to address N of the memory chips in the memory system. Similarly, in response to receiving a column-write request to write to column M in the matrix, the computer system rotates the column right by M elements, and writes the column in parallel to the memory chips in the memory system.

Abstract: A multiple access Proximity Communication system in which electrical elements on an integrated circuit chip provide the multiplexing of multiple signals to a single electrical receiving element on another chip. Multiple pads formed on one chip and receiving separate signals may be capacitively coupled to one large pad on the other chip. Multiple inductive coils on one chip may be magnetically coupled to one large coil on another chip or inductive coils on three or more chips may be used for either transmitting or receiving. The multiplexing may be based on time, frequency, or code.

Abstract: A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are adjacent to each other on the same side of a substrate in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. In addition, an input/output (I/O) integrated circuit is coupled to the optical integrated circuit between the substrate and the optical integrated circuit. This I/O integrated circuit includes high-speed I/O circuits and energy-efficient driver and receiver circuits and communicates with optical devices on the optical integrated circuit. By integrating the optical integrated circuit, the integrated circuit and the I/O integrated circuit in close proximity, the chip package may facilitate improved performance compared to chip packages with electrical interconnects.

Abstract: A method and apparatus for degassing an infant beverage are disclosed. A method for degassing an infant beverage applies ultrasonic energy to said infant beverage to remove gases dissolved therein. An apparatus for degassing an infant beverage includes a container for receiving an infant beverage defined by an inner wall and a base, a container for receiving an infant beverage, and an ultrasonic energy source positioned to transmit ultrasonic energy into the container and into the infant beverage received in the container to remove gases dissolved in said infant beverage. A medium for transduction of the ultrasonic signal may be arranged between a bottle in which an infant beverage is received and the inner wall of the container. A heater may be coupled to the container to heat or maintain the infant beverage at an optimal temperature while said infant beverage is received in said container.

Abstract: The disclosed embodiments provide a chip package that facilitates configurable-width memory channels. In this chip package, a semiconductor die is electrically connected to two or more memory chips. More specifically, contacts on each individual memory chip are each directly connected to a distinct set of contacts on the semiconductor die such that the semiconductor die has separate, unique command and address buses to individually address and communicate with each individual memory chip. Individually addressable memory chips that are each accessed via separate command and address buses facilitate a configurable-width memory channel that efficiently supports different data-access granularities.

Abstract: An ultrasonic probe (10) that scans a subject with beams of high frequency sound. The probe (10) includes a transducer (26) to produce high frequency sound waves, a means to steer the sound waves in the proper direction, a printed circuit board (22) with a non-volatile memory (38), a micro electrico-mechanical accelerometer integrated circuit (32) and an outlet connector (19). The accelerometer (32) is configured to detect the movement of the probe (10) in from two to three axes when the probe (10) is rotated or moved in a linear direction to allow the probe (10) to detect images from more than one plane.

Abstract: A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are proximate to each other in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a top surface of an interposer, and this top surface is in turn electrically coupled to a front surface of an input/output (I/O) integrated circuit that faces the top surface. Furthermore, the front surface of the I/O integrated circuit is electrically coupled to a top surface of the optical integrated circuit, where the top surface of the optical integrated circuit faces the front surface of the I/O integrated circuit.

Abstract: A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are adjacent to each in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a front surface of the optical integrated circuit by a top surface of the interposer, where the top surface faces the front surface of the integrated circuit and the front surface of the optical integrated circuit. Furthermore, the integrated circuit and the optical integrated circuit may be on a same side of the interposer. By integrating the optical integrated circuit and the integrated circuit in close proximity, the chip package may facilitate improved performance compared to chip packages with electrical interconnects.

Abstract: Offset voltages developed on floating nodes on inputs to high-performance amplifiers that are DC isolated from the data signals input to amplifiers are cancelled by connecting a highly resistive element between the input node and a predetermined potential, particularly useful in proximity communication systems in which two chips are connected through capacitive or inductive coupling circuits formed jointly in the two chips. The resistive element may be an off MOS transistor connected between the node and a desired bias voltage or a MOS transistor with its gate and drain connected to the potential. Multiple bias voltages may be distributed to all receivers and locally selected by a multiplexer for application to one or two input nodes of the receiver. The receiver output can also serve as a predetermined potential when the resistive element has a long time constant compared to the data rate or the resistive element is non-linear.

Abstract: A circuit that receives input signals from a transmitter via proximity communication, such as capacitively coupled proximity communication, is described. Because proximity communication may block DC content, the circuit may restore the DC content of input signals. In particular, a refresh circuit in the circuit may short inputs of the circuit to each other at least once per clock cycle (which sets a null value). Furthermore, a feedback circuit ensures that, if there is a signal transition in the input signals during a current clock cycle, it is passed through to an output node of the circuit. On the other hand, if there is no signal transition in the input signals during the current clock cycle, the feedback circuit may select the appropriate output value on the output node based on the output value during the immediately preceding clock cycle.

Abstract: The disclosed embodiments provide a chip package that facilitates configurable-width memory channels. In this chip package, a semiconductor die is electrically connected to two or more memory chips. More specifically, contacts on each individual memory chip are each directly connected to a distinct set of contacts on the semiconductor die such that the semiconductor die has separate, unique command and address buses to individually address and communicate with each individual memory chip. Individually addressable memory chips that are each accessed via separate command and address buses facilitate a configurable-width memory channel that efficiently supports different data-access granularities.

Abstract: Offset voltages developed on floating nodes on inputs to high-performance amplifiers that are DC isolated from the data signals input to amplifiers are cancelled by connecting a highly resistive element between the input node and a predetermined potential, particularly useful in proximity communication systems in which two chips are connected through capacitive or inductive coupling circuits formed jointly in the two chips. The resistive element may be an off MOS transistor connected between the node and a desired bias voltage or a MOS transistor with its gate and drain connected to the potential. Multiple bias voltages may be distributed to all receivers and locally selected by a multiplexer for application to one or two input nodes of the receiver. The receiver output can also serve as a predetermined potential when the resistive element has a long time constant compared to the data rate or the resistive element is non-linear.

Abstract: Techniques are described for performing grouping and aggregation operations. In an embodiment, a request is received to aggregate data grouped by a first column. In response to receiving the request, values are loaded from the first column into an input cache. The values include values, from the first column, from a set of rows. A filter unit is programmed with logic to perform a comparison between a particular value, from the first column of a first row, and values in the first column of a plurality of rows, of the set of rows. Based on the comparison, a predicate result is generated that identifies rows, within the plurality of rows, that have a valued in the first column that matches the particular value. An aggregate value for a second column is generated by aggregating values, from the second column, of each of the rows identified by the predicate result.

Abstract: Techniques are described for performing grouping and aggregation operations. In one embodiment, a request is received to aggregate data grouped by a first column. In response to receiving the request, a group value in a row of a first column is mapped to an address. A pointer is stored for a first group at a first location identified by the address. The pointer identifies a second location of a set of aggregation data for the first group. An aggregate value included in the set of aggregation data is updated based on a value in the row of a second column.

Abstract: Techniques are described for performing filter and project operations. In an embodiment, a set of predicates that specify criteria for filtering results to a query is received. Based on a particular predicate of the set of predicates, a predicate result for at least one portion of a particular column is generated. The predicate result identifies rows within the first column that satisfy the particular predicate. Rows are selected and returned as results to the query based at least in part on the predicate result. In an embodiment, the predicate result is a bitvector where each bit of the bitvector corresponds to a particular row within the particular column and identify whether the particular row satisfies the particular predicate.