Abstract: Described example embodiments include an integrated circuit having a first channel area with a first FET formed in a semiconductor substrate, the substrate providing a contact to the drain. A second channel area includes a second FET formed in the semiconductor substrate. A pilot FET couples to the first FET in a current mirror configuration. A third FET has a conductivity opposite the first and second FETs and couples to the source of the pilot FET. An op amp includes an output coupled to the gate of the third FET. Signals from the drain of the second FET and the source of the pilot FET couple to the inverting input of the op amp. Signals from the source of the first FET and the drain of the first FET couple to the non-inverting input of the op amp. Methods and additional apparatus are disclosed.

Abstract: A switch controller, an isolated system incorporating an integrated circuit (IC) and a method of operating a power switch. In one embodiment, the IC includes: (1) a monolithic substrate, (2) a drive circuit supported by the monolithic substrate and configured to drive a power switch, (3) a diagnostics block supported by the monolithic substrate and configured to provide diagnostic signals indicating at least one attribute associated with the power switch and (4) a control block supported by the monolithic substrate and configured to drive the drive circuit in response to control signals developed based on the diagnostic signals.

Abstract: A system that delivers power between a common power source having a total deliverable system power and device loads. The system includes a power share interface that sums power consumed or requested by loads and determines availability of additional power. The system includes at least one peer power share interface with each peer interface associated with a port controller and communicable coupled to the power share interface over the system bus. The peer power share interface determines status of total power consumed or requested relative to total deliverable system power. The power share interface can in response to receiving the power level request cause the system to change power allocations to satisfy the power level requests.

Abstract: A semiconductor device includes an output switching device having an input node, an output node, and a control input node. The control input node enables an input voltage applied to the input node to be switched to the output node. A gate pull-down circuit controls the control input node of the output switching device in response to at least one control signal. The gate pull-down circuit activates the output switching device by raising the voltage level of the control input node above the voltage level of the output node and deactivates the output switching device by clamping the control input node to the voltage level of the output node. A gate pull-up circuit receives an enable signal and generates the at least one control signal to the gate pull-down circuit in response to the enable signal.

Abstract: A switch controller, an isolated system incorporating an integrated circuit (IC) and a method of operating a power switch. In one embodiment, the IC includes: (1) a monolithic substrate, (2) a drive circuit supported by the monolithic substrate and configured to drive a power switch, (3) a diagnostics block supported by the monolithic substrate and configured to provide diagnostic signals indicating at least one attribute associated with the power switch and (4) a control block supported by the monolithic substrate and configured to drive the drive circuit in response to control signals developed based on the diagnostic signals.

Abstract: A semiconductor device and a method of making are disclosed. The device includes a substrate, a power field effect transistor (FET), and integrated sensors including a current sensor, a high current fault sensor, and a temperature sensor. The structure of the power FET includes a drain contact region of a first conductivity type disposed in the substrate, a drain drift region of the first conductivity type disposed over the drain contact region, doped polysilicon trenches disposed in the drain drift region, a body region of a second conductivity type, opposite from the first conductivity type, disposed between the doped polysilicon trenches, a source region disposed on a lateral side of the doped polysilicon trenches and in contact with the body region, and a source contact trench that makes contact with the source region and with the doped polysilicon trenches.

Abstract: A semiconductor device and a method of making are disclosed. The device includes a substrate, a power field effect transistor (FET), and integrated sensors including a current sensor, a high current fault sensor, and a temperature sensor. The structure of the power FET includes a drain contact region of a first conductivity type disposed in the substrate, a drain drift region of the first conductivity type disposed over the drain contact region, doped polysilicon trenches disposed in the drain drift region, a body region of a second conductivity type, opposite from the first conductivity type, disposed between the doped polysilicon trenches, a source region disposed on a lateral side of the doped polysilicon trenches and in contact with the body region, and a source contact trench that makes contact with the source region and with the doped polysilicon trenches.

Abstract: Described example embodiments include an integrated circuit having a first channel area with a first FET formed in a semiconductor substrate, the substrate providing a contact to the drain. A second channel area includes a second FET formed in the semiconductor substrate. A pilot FET couples to the first FET in a current mirror configuration. A third FET has a conductivity opposite the first and second FETs and couples to the source of the pilot FET. An op amp includes an output coupled to the gate of the third FET. Signals from the drain of the second FET and the source of the pilot FET couple to the inverting input of the op amp. Signals from the source of the first FET and the drain of the first FET couple to the non-inverting input of the op amp. Methods and additional apparatus are disclosed.

Abstract: A semiconductor device includes an output switching device having an input node, an output node, and a control input node. The control input node enables an input voltage applied to the input node to be switched to the output node. A gate pull-down circuit controls the control input node of the output switching device in response to at least one control signal. The gate pull-down circuit activates the output switching device by raising the voltage level of the control input node above the voltage level of the output node and deactivates the output switching device by clamping the control input node to the voltage level of the output node. A gate pull-up circuit receives an enable signal and generates the at least one control signal to the gate pull-down circuit in response to the enable signal.

Abstract: Circuits and methods for driving ERM motors are disclosed herein. An embodiment of the circuit includes an input, wherein an input signal is receivable at the input and a back EMF signal. The circuit operates in a closed loop mode when the back EMF signal is less than a lower threshold value and the difference between the value of the input signal and the back EMF signal indicates that the velocity of the motor needs to increase. The circuit operates in an open loop mode when the back EMF signal is greater than a high threshold value and the difference between the value of the input signal and the back EMF signal indicates that the velocity of the motor needs to increase.

Abstract: A method for driving a Linear Resonant Actuator (LRA) is provided. During a first off interval, the back-emf of the LRA is measured. During a first off interval, a timer is started when the back-emf reaches a predetermined threshold, and after a predetermined delay has lapsed following the back-emf reaching the predetermined threshold during the first off interval, the LRA is driven over a drive interval having a length and drive strength. A second off interval is entered following the drive interval, and during the second off interval, the back-emf of the LRA is measured. During the second off interval, the timer is stopped when the back-emf reaches the predetermined threshold. The value from the timer that corresponds to the duration between the back-emf reaching the predetermined threshold during the first off interval and the back-emf reaching the predetermined threshold during the second off interval determines the length.

Abstract: A method for driving a Linear Resonant Actuator (LRA) is provided. During a first off interval, the back-emf of the LRA is measured. During a first off interval, a timer is started when the back-emf reaches a predetermined threshold, and after a predetermined delay has lapsed following the back-emf reaching the predetermined threshold during the first off interval, the LRA is driven over a drive interval having a length and drive strength. A second off interval is entered following the drive interval, and during the second off interval, the back-emf of the LRA is measured. During the second off interval, the timer is stopped when the back-emf reaches the predetermined threshold. The value from the timer that corresponds to the duration between the back-emf reaching the predetermined threshold during the first off interval and the back-emf reaching the predetermined threshold during the second off interval determines the length.

Abstract: A method for driving a piezoelectric transducer is provided. An input signal is received. At least one of a plurality of modes is selected for a buck-boost stage from a comparison of a desired voltage on a capacitor to a first threshold and a second threshold, where the desired voltage is determined from the input signal. The piezoelectric transducer is then driven substantially within the audio band using the desired voltage on the capacitor using an H-bridge that changes state with each zero-crossing.

Abstract: Circuits and methods for driving ERM motors are disclosed herein. An embodiment of the circuit includes an input, wherein an input signal is receivable at the input and a back EMF signal. The circuit operates in a closed loop mode when the back EMF signal is less than a lower threshold value and the difference between the value of the input signal and the back EMF signal indicates that the velocity of the motor needs to increase. The circuit operates in an open loop mode when the back EMF signal is greater than a high threshold value and the difference between the value of the input signal and the back EMF signal indicates that the velocity of the motor needs to increase.

Abstract: An apparatus and method are provided. Generally, an input signal is applied across a main path (through an input network) and across a cancellation path (through a cancellation circuit). The cancellation circuit subtracts a cancellation current from the main path as part of the control mechanism, where the magnitude of the cancellation current is based on a gain control signal (that has been linearized to follow a control voltage).

Abstract: A method for driving a piezoelectric transducer is provided. An input signal is received. At least one of a plurality of modes is selected for a buck-boost stage from a comparison of a desired voltage on a capacitor to a first threshold and a second threshold, where the desired voltage is determined from the input signal. The piezoelectric transducer is then driven substantially within the audio band using the desired voltage on the capacitor using an H-bridge that changes state with each zero-crossing.

Abstract: A method for driving a Linear Resonant Actuator (LRA) is provided. During a first off interval, the back-emf of the LRA is measured. During a first off interval, a timer is started when the back-emf reaches a predetermined threshold, and after a predetermined delay has lapsed following the back-emf reaching the predetermined threshold during the first off interval, the LRA is driven over a drive interval having a length and drive strength. A second off interval is entered following the drive interval, and during the second off interval, the back-emf of the LRA is measured. During the second off interval, the timer is stopped when the back-emf reaches the predetermined threshold. The value from the timer that corresponds to the duration between the back-emf reaching the predetermined threshold during the first off interval and the back-emf reaching the predetermined threshold during the second off interval determines the length.

Abstract: An apparatus and method are provided. Generally, an input signal is applied across a main path (through an input network) and across a cancellation path (through a cancellation circuit). The cancellation circuit subtracts a cancellation current from the main path as part of the control mechanism, where the magnitude of the cancellation current is based on a gain control signal (that has been linearized to follow a control voltage).

Abstract: An apparatus and method are provided. Generally, an input signal is applied across a main path (through an input network) and across a cancellation path (through a cancellation circuit). The cancellation circuit subtracts a cancellation current from the main path as part of the control mechanism, where the magnitude of the cancellation current is based on a gain control signal (that has been linearized to follow a control voltage).

Abstract: Traditionally, switching amplifiers (i.e., class-D and class-G) with negative supply rails had issues with direct current (DC) power loss, included large external capacitors, had a comparative reduction in efficiency, and oftentimes included separate power management circuits. Here, a class-D amplifier is provided with an output stage that provides negative supply voltages, positive supply voltages, and ground. Essentially, this amplifier provides some of the benefits of the conventional amplifiers without the drawbacks.