Abstract: A controlled area network (CAN) driver provides improved symmetry between its differential output signals CAN-H and CAN-L, and provides protection for its low voltage devices from voltage transients occurring on its output lines. A plurality of CAN drivers 80 are serially interconnected to form a driver system, wherein each downstream driver stage receives a time-delayed form of the digital input signal TxD, each stage providing a time-delayed contribution to the differential output signals of the overall driver system.

Abstract: A variable transconductance current mirror circuit includes a first field effect transistor having a gate, a source, and a drain, and a second field effect transistor having a gate, a source, and a drain. The gate of the second transistor is coupled to the gate of the first transistor, and a current source is coupled to the gates of the first and second transistors. The circuit also includes a voltage supply coupled to the sources of the first and second transistors. The circuit further includes a first diode having an anode and a cathode. The anode of the first diode is coupled to the gates of the first and second transistors, and the cathode of the first diode is coupled to the source of the first and second transistors. The first diode comprises a zener diode having a reverse breakdown voltage operable to prevent gate oxide breakdown of the first and second transistors.

Abstract: An integrated circuit having a protected output field effect transistor (FET) (101). A drain-gate clamp circuit (105) is coupled to divert charge from the power FET drain electrode to the power FET gate electrode when excessive drain-source voltage is present. A drain-source current limit circuit (110) is coupled to divert charge from the power FET gate electrode to the power FET source electrode when a preselected drain-source current is achieved. A current limit inhibit circuit (115) is coupled between the current limit circuit and the power FET gate electrode, and having a control electrode coupled to the drain-gate clamp circuit. The current limit inhibit circuit (115) disables the current limit circuit (110) when charge flows in the drain-gate clamp circuit (105).

Abstract: A circuit for protecting a transistor against electrical transients. The circuit comprises a first diode coupled between a first terminal coupled to a power supply and a control terminal of the protected transistor. The circuit also comprises a second diode and a resistor coupling the control terminal of the protected transistor to a reference potential. A second transistor is coupled in shunt to the protected transistor. The voltage on the control terminal of the second transistor is determined by the current through the resistor. The embodiments may be implemented in an integrated circuit wherein the second, shunting transistor is formed from parasitic elements within the semiconductor body in which the protected transistor is formed. In one embodiment, the protected MOS transistor is formed in an n-well 504 and a shunting bipolar transistor is formed between the n-well 504 and an n-doped guard ring 500 formed adjacent to the n-well in the p-doped substrate 508.

Abstract: A transistor including a source region 506 in a semiconductor body 502; a bulk region 508 in the semiconductor body adjacent the source region; a drain region in the semiconductor body adjacent the bulk region but opposite the source region, the drain region including doped regions 504,514 of n and p dopant types; and a field plate 516 formed over the semiconductor body adjacent the drain region between the drain region and the bulk region.

Abstract: An internal circuitry protection scheme which protects on-IC circuitry when an external regulator voltage pin is shorted to a higher voltage. The circuit prevents damage to the on-die circuitry that is on the internal voltage rail, by clamping the received voltage, thereby eliminating the chance of damaging the on die circuitry. The circuit offers protection even if the voltage difference is large, but the difference remains small between the internal rail and the external regulated voltage under normal operation.

Abstract: A high-side MOSFET gate protection shunt circuit is provided for protecting an output driving transistor (10). The output driving transistor (10) is operable to drive a load (18) on an output node (12). A sense resistor (26) is disposed between the supply voltage terminal and the output node (12). The gate of transistor (10) is driven by a current limited driver (20). In order to prevent the voltage across the gate oxide of transistor (10) from exceeding a predetermined voltage above which would be destructive to the transistor, a bypass transistor (32) is disposed between the output of the MOSFET driver (14) and the supply terminal (11). The gate of this transistor (32) is connected to the output node (12), such that the voltage on the gate of transistor (10) is limited to one threshold voltage below the voltage on the output node (12).