Abstract: Audio amplifiers and methods of generating audio signals are disclosed. A disclosed example amplifier comprises a first driver to receive a first signal; a second driver to receive a second signal; a configurable signal delivery circuit; and a mode selector in communication with the first and second drivers to selectively configure the signal delivery circuit in a voltage boost mode or a voltage buck-boost mode based on a characteristic of the input signal.

Abstract: Audio amplifiers and methods of generating audio signals are disclosed. A disclosed example amplifier comprises a first driver to receive a first signal; a second driver to receive a second signal; a configurable signal delivery circuit; and a mode selector in communication with the first and second drivers to selectively configure the signal delivery circuit in a voltage boost mode or a voltage buck-boost mode based on a characteristic of the input signal.

Abstract: Methods and apparatus to detect impedance at an amplifier output are described. In one example, a method of determining a relative value of an amplifier output load may include determining a current provided to the amplifier output load in response to an input signal; determining a current provided to a reference load in response to a signal based on the input signal; comparing the current provided to the amplifier output load to the current provided to the reference load; and indicating a relationship between the amplifier output load and the reference load based on the current provided to the amplifier output load and the current provided to the reference load.

Abstract: Methods and apparatus to detect impedance at an amplifier output are described. In one example, a method of determining a relative value of an amplifier output load may include determining a current provided to the amplifier output load in response to an input signal; determining a current provided to a reference load in response to a signal based on the input signal; comparing the current provided to the amplifier output load to the current provided to the reference load; and indicating a relationship between the amplifier output load and the reference load based on the current provided to the amplifier output load and the current provided to the reference load.

Abstract: A system and method for driving a load at a desired operating level. A driver is connected to a load. The load can be selected from a plurality of loads by a selection system, such as a multiplexer, or a single load can be utilized. Feedback from the load is provided to the driver for achieving the desired operating level. A zero temperature coefficient resistance formed by two resistors having different resistances can be used so that the driver emulates an ideal resistor having a substantially zero temperature coefficient, providing a temperature independent current to the load.

Abstract: A current control device for driving LED devices uses a switched-mode current control loop inside of an output intensity low-frequency pulse width modulation (PWM) control loop. This allows separate control of current level (for accurate light wavelength output) and light intensity. The current control device requires only one switch to regulate current level, and no other switches for the intensity control. This allows lower parts count for greater reliability and lower system cost.

Abstract: A system and method are provided to regulate resistance in a discontinuous time hot-wire anemometer. The solution removes supply voltage dependency on the mass airflow output signal. Operating the hot-wire anemometer using discontinuous time regulation offers lower system power, but introduces an inverse supply dependent term in the associated transfer function. This effect is removed by multiplying the output signal via a supply dependent signal.

Abstract: The present invention provides a system for limiting energy levels across the output of a driver circuitry segment (100). The system provides an output structure (102) adapted to drive an output load (104). A transconductance component (106) is communicatively coupled to the output structure, and adapted to output a transconductance current that is proportional to the voltage across the output structure. A scaling component (108) is communicatively coupled to the output structure, and adapted to output a scaled current that is proportional, by some scaling factor, to the current through the output structure. A qualifying component (110) is communicatively coupled to the scaling component, and adapted to activate a trigger component (112) when the scaled current passes a first threshold. The trigger component is communicatively coupled to the qualifying component, the transconductance component, and the output structure.

Abstract: In accordance with the teachings of the present invention, a system and method for regulating bridge voltage in a discrete-time hot-wire anemometer is provided. In a particular embodiment, the hot-wire anemometer includes a bridge circuit including a hot-wire resistor, first and second input terminals, and first and second output terminals, the hot-wire resistor having a resistance dependent at least in part on an airflow past the hot-wire resistor. The hot-wire anemometer further includes a first operational amplifier coupled to the output terminals of the bridge circuit, the first operational amplifier operable to generate an output signal in response to a voltage differential across the first and second output terminals of the bridge circuit, and a second operational amplifier operable to generate an output signal in response to the output signal of the first operational amplifier and to a discontinuous time control signal.

Abstract: A synchronous DC-DC regulator, adapted to receive a high side pulsed signal and a low side pulsed signal that is substantially the inverse of the high side pulsed signal. The regulator includes an inductor, and a capacitor having one port connected to ground, and having a second port providing an output voltage of the DC-DC regulator. A driver is provided for driving pulses of current to the inductor when the high side pulsed signal is asserted. An undercurrent sense circuit is adapted to sense a driving current flowing through the driver and to assert a disable signal when the driving current is less than a predetermined amount. An enable/disable circuit is adapted to allow the low side pulsed signal to turn the switch on when the disable signal is not asserted, and to not allow the low side pulsed signals from turning the switch on when the disable signal is asserted.

Abstract: A switching regulator having a control circuit that automatically senses when a low power mode should be initiated without the use of expensive external components nor an extensive amount of external components is disclosed herein. The switching regulator includes an input switching device, a driver, an inductor, a first output switching device, a second output switching device and an output node. The control circuit includes a low power switching device connected to the output node and the second end of the inductor. An amplifier connects the low power switching device and the first output switching device. A first current mirror couples to the amplifier to mirror the difference between the output current through the output load and the current supplied at the second end of the inductor. A second current mirror couples to the first current mirror to mirror the current difference through a current source and a capacitor connected in parallel across the current source.

Abstract: A DC/DC converter has a semiconductor switch coupled to an inductor, a capacitor and a rectifier. A comparator is coupled to across the rectifier to detect a polarity reversal during the second portion of converter operation to place the converter in a low power mode if the voltage across the rectifier is of an appropriate polarity for reverse current flow. The rectifier may be a synchronous rectifier transistor and the voltage converter placed in a low power mode when the polarity across the synchronous rectifier indicates that reverse current flow is possible. A timing circuit delays the generation of the control signal to place the converter in a low power mode until the steady state current is below a predetermined threshold for a predetermined amount of time.

Abstract: A DC/DC converter has a semiconductor switch coupled to an inductor, a capacitor and a rectifier. A comparator is coupled to across the rectifier to detect a polarity reversal during the second portion of converter operation to place the converter in a low power mode if the voltage across the rectifier is of an appropriate polarity for reverse current flow. In some embodiments of the invention, the rectifier is a synchronous rectifier transistor and the voltage converter is placed in a low power mode when the polarity across the synchronous rectifier indicates that reverse current flow is possible. A timing circuit delays the generation of the control signal to place the converter in a low power mode until the steady state current is below a predetermined threshold for a predetermined amount of time.

Abstract: A synchronous DC-DC regulator, adapted to receive a high side pulsed signal and a low side pulsed signal that is substantially the inverse of the high side pulsed signal. The regulator includes an inductor, and a capacitor having one port connected to ground, and having a second port providing an output voltage of the DC-DC. A driver is provided for driving pulses of current to the inductor when the high side pulsed signal is asserted. A switch and a diode are provided, adapted to provide a path for the inductor to drive current to charge the capacitor when the high side pulsed signal is not asserted. An undercurrent sense circuit is adapted to sense a driving current flowing through the driver and to assert a disable signal when the driving current is less than a predetermined amount.

Abstract: A switch mode controller circuit includes: a hysteretic comparator HYST_COMP for monitoring an output of a switch mode circuit; a standard comparator PHASE_COMP for monitoring a phase of the switch mode circuit; a logic block having a first input coupled to a clock signal generator Oscillator, a second input coupled to an output of the hysteretic comparator HYST_COMP, and a third input coupled to an output of the standard comparator PHASE_COMP, wherein the logic block generates switching cycles based on a fixed ON/OFF time during a first part of a cycle and based on a hysteretic control during a second part of the cycle.

Abstract: An integrated solution to power management and distribution on a power bus, such as needed for an IEEE 1394 compliant expansion board. The integrated circuit includes a uni-directional switch on the input and one or more bi-directional switches on one or more outputs. Current can flow from the system power supply to any connected peripherals via the uni-directional switch and bi-directional switches, or can flow from the peripheral having the highest voltage power supply to the other peripherals via the bi-directional switches, but current will not flow back to the main system because of the unidirectional switch connected to the system power supply. Over-current conditions are quickly detected and the bi-directional switch is opened to prevent damage or over-heating. The switches are preferably fabricated as power FETs using NMOS technology. Several integrated circuits can be cascaded together to accommodate multiple peripherals.

Abstract: A multiple mode switching regulator with a bootstrap technique includes an inductor 20; a high side input switch 22 coupled to a first end of the inductor 20; a low side input switch 24 coupled to the first end of the inductor 20; a high side driver 34 coupled to a control node of the high side input switch 22; a low side driver 36 coupled to a control node of the low side input switch 24; a high side output switch 26 coupled to a second end of the inductor 20; a low side output switch 28 coupled to the second end of the inductor 20; a first bootstrap capacitor 30 coupled between the first end of the inductor 20 and a voltage supply node of the high side driver 34; a second bootstrap capacitor 32 coupled between the second end of the inductor 20 and a voltage supply node of the low side driver 36; and a first diode 40 coupled between the voltage supply node of the high side driver 34 and the voltage supply node of the low side driver 36.

Abstract: A control circuit (50) for a switch mode power converter having precise control of amplitude and frequency that does not exhibit overshoot error nor undershoot error during a fast charge cycle nor a fast discharge cycle, respectively. In a first embodiment, the control circuit (50) does not exhibit undershoot error during a fast discharge cycle. The control circuit (50) comprises an oscillator (70) for providing a periodic carrier signal comprising a sawtooth wave output signal (VST). The oscillator (70) includes a capacitor (CT2) charged and discharged to the power supply voltage (VCC) to provide the sawtooth wave output signal (VST). In addition, the oscillator (70) includes a switching circuit (65) coupled to the reference voltage level (Vref). The control circuit (50) further includes a gain circuit (64) having a reference voltage input (Vref2), voltage input (Vin) and an output (Out). The reference voltage input (Vref2) receives the reference voltage(Vref).

Abstract: One aspect of the invention is an integrated circuit (10 or 110) comprising an amplifier (11 or 111) having at least two poles in its frequency response and an output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) coupled to an output node (30) of the amplifier (11 or 111). The output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) is operable to create a feedback signal proportional to the impedance of an output load (50) coupled to the output node (30), and create a zero in the frequency response of the amplifier (11 or 111) in response to the feedback signal between the at least two poles.

Abstract: An integrated circuit (10) is disclosed comprising a fundamental frequency oscillator comprising a reference node (32) whose voltage varies between a high threshold and a low threshold. The fundamental frequency oscillator is operable to generate a first output at the fundamental frequency on a first output node (36). The integrated circuit (10) also comprises a circuit (C2) coupled to the reference node. The circuit (C2) is operable to sense the voltage at the reference node (32), to determine when the voltage exceeds an intermediate threshold between the high threshold and the low threshold, and to generate a second output in response to the determination. The integrated circuit (10) also comprises logic (40) coupled to the circuit (C2) and load circuitry (50) coupled to the logic (40). The logic (40) is operable to generate an output signal at an output frequency greater than the fundamental frequency in response to the second output and the first output.