Patents by Inventor David J. Hathaway
David J. Hathaway has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11301600Abstract: Generating a contributor-based power abstract for a device, including: identifying a clock power component for each of a plurality of clock gating domains, identifying a switching characteristic for each of the clock gating domains, combining the switching characteristics for all of the clock gating domains into a domain combination list, performing a per-case simulation based at least on the domain combination list, calculating an effective capacitance for each of the clock gating domains based at least on the per-case simulation, and generating a power abstract for each of the clock gating domains based at least on the effective capacitance.Type: GrantFiled: August 7, 2019Date of Patent: April 12, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nagashyamala R. Dhanwada, William W. Dungan, David J. Hathaway, Arun Joseph, Gaurav Mittal, Ricardo H. Nigaglioni
-
Publication number: 20190362040Abstract: Generating a contributor-based power abstract for a device, including: identifying a clock power component for each of a plurality of clock gating domains, identifying a switching characteristic for each of the clock gating domains, combining the switching characteristics for all of the clock gating domains into a domain combination list, performing a per-case simulation based at least on the domain combination list, calculating an effective capacitance for each of the clock gating domains based at least on the per-case simulation, and generating a power abstract for each of the clock gating domains based at least on the effective capacitance.Type: ApplicationFiled: August 7, 2019Publication date: November 28, 2019Inventors: NAGASHYAMALA R. DHANWADA, WILLIAM W. DUNGAN, DAVID J. HATHAWAY, ARUN JOSEPH, GAURAV MITTAL, RICARDO H. NIGAGLIONI
-
Patent number: 10460048Abstract: Generating a contributor-based power abstract for a device, including: identifying a clock power component for each of a plurality of clock gating domains, identifying a switching characteristic for each of the clock gating domains, combining the switching characteristics for all of the clock gating domains into a domain combination list, performing a per-case simulation based at least on the domain combination list, calculating an effective capacitance for each of the clock gating domains based at least on the per-case simulation, and generating a power abstract for each of the clock gating domains based at least on the effective capacitance.Type: GrantFiled: July 1, 2015Date of Patent: October 29, 2019Assignee: International Business Machines CorporationInventors: Nagashyamala R. Dhanwada, William W. Dungan, David J. Hathaway, Arun Joseph, Gaurav Mittal, Ricardo H. Nigaglioni
-
Patent number: 10210297Abstract: A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.Type: GrantFiled: December 7, 2016Date of Patent: February 19, 2019Assignee: International Business Machines CorporationInventors: David J. Hathaway, Nathaniel D. Hieter, Shyam Ramji, Alexander J. Suess
-
Patent number: 9985843Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.Type: GrantFiled: February 27, 2015Date of Patent: May 29, 2018Assignee: International Business Machines CorporationInventors: Hemlata Gupta, David J. Hathaway, Kerim Kalafala, Ronald D. Rose
-
Publication number: 20180121595Abstract: A method may include: specifying a random nets credit (RNC) statistic for nets subject to random noise in a static timing analysis of an initial integrated circuit (IC) design; calculating an upper bound for a delta delay of each net using the RNC statistic; identifying each net with a delta delay that exceeds the upper bound; identifying all nets including fan-in and fan-out cones connected to each net that exceeds the upper bound and performing a higher accuracy timing analysis for all nets that are marked. Using the upper bound for each delta delay of the nets subject to ransom noise, the delta delay of each net subject to a non-random noise, and the delta delay for all identified nets, to adjust the initial IC design, to close timing and generate a final IC design.Type: ApplicationFiled: November 2, 2017Publication date: May 3, 2018Applicant: International Business Machines CorporationInventors: David J. Hathaway, Ronald D. Rose
-
Patent number: 9864824Abstract: A computer program product for performing selected timing comparisons in a digital electronic design includes propagating from signal sources to timing comparisons of one or multiple signal labels. The signal label includes signal source identifiers and signal path cycle adjust information. Timing comparisons are determined in which signal label values at each input of the timing comparison are required to compute the selected timing comparisons. The propagation back from the timing comparisons are needed signal labels, followed by the propagation and computing timing data from the signal source applied to the propagated signal labels corresponding to the required signal labels.Type: GrantFiled: December 1, 2015Date of Patent: January 9, 2018Assignee: International Business Machines CorporationInventors: David J. Hathaway, Kerim Kalafala, Stephen G. Shuma, Chandramouli Visweswariah
-
Patent number: 9853866Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.Type: GrantFiled: January 10, 2017Date of Patent: December 26, 2017Assignee: International Business Machines CorporationInventors: Hemlata Gupta, David J. Hathaway, Kerim Kalafala, Ronald D. Rose
-
Patent number: 9852246Abstract: A system performing selected timing comparisons in a digital electronic design includes propagating from signal sources to timing comparisons of one or multiple signal labels. The signal label includes signal source identifiers and signal path cycle adjust information. Timing comparisons are determined in which signal label values at each input of the timing comparison are required to compute the selected timing comparisons. The propagation back from the timing comparisons are needed signal labels, followed by the propagation and computing timing data from the signal source applied to the propagated signal labels corresponding to the required signal labels.Type: GrantFiled: December 1, 2015Date of Patent: December 26, 2017Assignee: International Business Machines CorporationInventors: David J. Hathaway, Kerim Kalafala, Stephen G. Shuma, Chandramouli Visweswariah
-
Patent number: 9836571Abstract: A method may include: specifying a random nets credit (RNC) statistic for nets subject to random noise in a static timing analysis of an initial integrated circuit (IC) design; calculating an upper bound for a delta delay of each net using the RNC statistic; identifying each net with a delta delay that exceeds the upper bound; identifying all nets including fan-in and fan-out cones connected to each net that exceeds the upper bound and performing a higher accuracy timing analysis for all nets that are marked. Using the upper bound for each delta delay of the nets subject to ransom noise, the delta delay of each net subject to a non-random noise, and the delta delay for all identified nets, to adjust the initial IC design, to close timing and generate a final IC design.Type: GrantFiled: June 23, 2015Date of Patent: December 5, 2017Assignee: International Business Machines CorporationInventors: David J. Hathaway, Ronald D. Rose
-
Patent number: 9785737Abstract: A method, system, and computer program product to perform parallel multi-threaded common path pessimism removal in integrated circuit design include constructing, using a processor, a thread-specific graphical representation (TSGR) relating to each data node and clock node pair and performing processes in parallel for each TSGR. The processes include determining initial arrival times at the data node and the clock node, computing initial test slack based on the initial arrival times at the data node and the clock node, identifying fan-out nodes among the additional nodes, each fan-out node being an origin of at least two of the edges in the two or more paths to the clock node, generating one or more tags based the fan-out nodes, determining adjusted arrival times based on the one or more tags, and computing adjusted test slack based on the adjusted arrival times.Type: GrantFiled: November 17, 2015Date of Patent: October 10, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David J. Hathaway, Kerim Kalafala, Vasant B. Rao, Alexander J. Suess, Vladimir Zolotov
-
Patent number: 9747400Abstract: A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.Type: GrantFiled: December 7, 2016Date of Patent: August 29, 2017Assignee: International Business Machines CorporationInventors: David J. Hathaway, Nathaniel D. Hieter, Shyam Ramji, Alexander J. Suess
-
Patent number: 9703914Abstract: A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.Type: GrantFiled: June 21, 2016Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: David J. Hathaway, Nathaniel D. Hieter, Shyam Ramji, Alexander J. Suess
-
Publication number: 20170140089Abstract: A method, system, and computer program product to perform parallel multi-threaded common path pessimism removal in integrated circuit design include constructing, using a processor, a thread-specific graphical representation (TSGR) relating to each data node and clock node pair and performing processes in parallel for each TSGR. The processes include determining initial arrival times at the data node and the clock node, computing initial test slack based on the initial arrival times at the data node and the clock node, identifying fan-out nodes among the additional nodes, each fan-out node being an origin of at least two of the edges in the two or more paths to the clock node, generating one or more tags based the fan-out nodes, determining adjusted arrival times based on the one or more tags, and computing adjusted test slack based on the adjusted arrival times.Type: ApplicationFiled: November 17, 2015Publication date: May 18, 2017Inventors: David J. Hathaway, Kerim Kalafala, Vasant B. Rao, Alexander J. Suess, Vladimir Zolotov
-
Patent number: 9639654Abstract: Managing virtual boundaries to enable lock-free concurrent region optimization, including: receiving a model of an integrated circuit (‘IC’); dividing the model into a plurality of regions, wherein none of the plurality of regions overlap with another region; assigning each of the plurality of regions to a thread of execution, wherein each thread of execution utilizes a shared memory space; and optimizing, by each thread in parallel, the assigned region.Type: GrantFiled: December 11, 2014Date of Patent: May 2, 2017Assignee: International Business Machines CorporationInventors: Bijian Chen, David J. Hathaway, Nathaniel D. Hieter, Kerim Kalafala, Jeffrey S. Piaget, Alexander J. Suess
-
Publication number: 20170111232Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.Type: ApplicationFiled: January 10, 2017Publication date: April 20, 2017Inventors: Hemlata Gupta, David J. Hathaway, Kerim Kalafala, Ronald D. Rose
-
Patent number: 9608868Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.Type: GrantFiled: September 16, 2016Date of Patent: March 28, 2017Assignee: International Business Machines CorporationInventors: Hemlata Gupta, David J. Hathaway, Kerim Kalafala, Ronald D. Rose
-
Publication number: 20170083641Abstract: A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.Type: ApplicationFiled: December 7, 2016Publication date: March 23, 2017Inventors: David J. Hathaway, Nathaniel D. Hieter, Shyam Ramji, Alexander J. Suess
-
Publication number: 20170083642Abstract: A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.Type: ApplicationFiled: December 7, 2016Publication date: March 23, 2017Inventors: David J. Hathaway, Nathaniel D. Hieter, Shyam Ramji, Alexander J. Suess
-
Patent number: 9542524Abstract: Disclosed are a system and a method for performing a timing analysis of an integrated circuit (IC). An internal timing constraint of a logic device in a first signal pathway of a hierarchical entity in an IC design is determined based on a reference value and, if necessary, on library information. A first boundary timing constraint associated with the first signal pathway is derived based on the internal timing constraint and a second boundary timing constraint associated with the first signal pathway is derived based on the first boundary timing constraint and a target slack value for the internal timing constraint. A static timing analysis is performed using the second boundary timing constraint. Based on the analysis, a timing abstraction for the hierarchical entity is generated. A timing model for the IC design is generated using the timing abstraction and other timing abstractions for other hierarchical entities in the design.Type: GrantFiled: January 27, 2015Date of Patent: January 10, 2017Assignee: International Business Machines CorporationInventors: James C. Gregerson, David J. Hathaway, Kerim Kalafala, Tsz-Mei Ko, Alex Rubin