Abstract: A method and a system performing selected timing comparisons in a digital electronic design includes propagating from signal sources to timing comparisons of one or multiple signal labels. The signal label includes signal source identifiers and signal path cycle adjust information. Timing comparisons are determined in which signal label values at each input of the timing comparison are required to compute the selected timing comparisons. The propagation back from the timing comparisons are needed signal labels, followed by the propagation and computing timing data from the signal source applied to the propagated signal labels corresponding to the required signal labels.

Abstract: Systems and methods for improving timing closure of new and existing semiconductor products by balancing sensitivities. More specifically, a method is provided for that includes defining at least one set of correlated parameters for a semiconductor product, the at least one set of correlated parameters comprising a first parameter and a second parameter. The method further includes measuring performance of embedded devices within the semiconductor product. The method further includes closing timing of the semiconductor product using the measured performance of the semiconductor product. The closing the timing of the semiconductor product comprises calculating a sensitivity to the first parameter based on the measured performance of the embedded devices within the semiconductor product and balancing the sensitivity to the first parameter with a sensitivity to a second parameter such that timing degradation is shifted from the first parameter to the second parameter.

Abstract: A method and a system of maintaining slack continuity in incremental statistical timing analysis includes using a computer to forward propagating both scalar and statistical arrival times in a single timing environment; computing for a timing end point one or more projected statistical slack value; computing a scalar reverse engineered required arrival time from the projected statistical slack value; back propagating the scalar reverse engineered required arrival time using scalar delay values, measuring a resulting slack and performing a redesign based on the reverse engineered scalar required arrival time and resulting slack; and incrementally re-executing selected steps to re-compute a new scalar reverse-engineered required arrival time and new resulting slack.

Abstract: A method and a system performing selected timing comparisons in a digital electronic design includes propagating from signal sources to timing comparisons of one or multiple signal labels. The signal label includes signal source identifiers and signal path cycle adjust information. Timing comparisons are determined in which signal label values at each input of the timing comparison are required to compute the selected timing comparisons. The propagation back from the timing comparisons are needed signal labels, followed by the propagation and computing timing data from the signal source applied to the propagated signal labels corresponding to the required signal labels.

Abstract: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation.

Abstract: Systems and methods for improving timing closure of new and existing semiconductor products by balancing sensitivities. More specifically, a method is provided for that includes defining at least one set of correlated parameters for a semiconductor product, the at least one set of correlated parameters comprising a first parameter and a second parameter. The method further includes measuring performance of embedded devices within the semiconductor product. The method further includes closing timing of the semiconductor product using the measured performance of the semiconductor product. The closing the timing of the semiconductor product comprises calculating a sensitivity to the first parameter based on the measured performance of the embedded devices within the semiconductor product and balancing the sensitivity to the first parameter with a sensitivity to a second parameter such that timing degradation is shifted from the first parameter to the second parameter.

Abstract: According to a method herein, a portion of an electronic circuit is identified. The electronic circuit comprises logic circuitry. The portion of the electronic circuit is designed in at least two versions. Each of the at least two versions is evaluated using a plurality of operating conditions. The current operating conditions are determined. One version of the at least two versions is identified as a selected version based on the performance under the current operating conditions. The selected version has relatively optimal performance based on at least one of clock frequency, supply voltage, and power limit. The selected version is activated for use in the portion of the electronic circuit. The remaining versions of the at least two versions are deactivated.

Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.

Abstract: Various embodiments include approaches for controlling a supply voltage or a clock frequency to an integrated circuit (IC). Various additional embodiments include circuitry for controlling a supply voltage or a clock frequency of an IC. In some cases, a method includes: locating a set of temperature sensors on bin locations in an IC; determining temperature bounds of the bin locations in the IC as a function of a determined temperature at the set of temperature sensors; determining timing constraints as a function of supply voltages at the bin locations and the determined temperature at the set of temperature sensors; and determining operational voltage bounds for the IC as a function of the determined temperature at the set of temperature sensors.

Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.

Abstract: Various embodiments include approaches for controlling a supply voltage or a clock frequency to an integrated circuit (IC). Various additional embodiments include circuitry for controlling a supply voltage or a clock frequency of an IC. In some cases, a method includes: locating a set of temperature sensors on bin locations in an IC; determining temperature bounds of the bin locations in the IC as a function of a determined temperature at the set of temperature sensors; determining timing constraints as a function of supply voltages at the bin locations and the determined temperature at the set of temperature sensors; and determining operational voltage bounds for the IC as a function of the determined temperature at the set of temperature sensors.

Abstract: A method for generating a power model for a device includes identifying a device-level set of power contributors for a given state of the device, wherein each power contributor in the device-level set of power contributors contributes to power dissipation when the device is in the given state, and generating the power model for the device based on the device-level set of power contributors, wherein the power model is independent of process, voltage, and temperature.

Abstract: According to a method herein, a portion of an electronic circuit is identified. The electronic circuit comprises logic circuitry. The portion of the electronic circuit is designed in at least two versions. Each of the at least two versions is evaluated using a plurality of operating conditions. The current operating conditions are determined. One version of the at least two versions is identified as a selected version based on the performance under the current operating conditions. The selected version has relatively optimal performance based on at least one of clock frequency, supply voltage, and power limit. The selected version is activated for use in the portion of the electronic circuit. The remaining versions of the at least two versions are deactivated.

Abstract: Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a color to each pattern shape in a first cell, assign a color to each pattern shape in a second cell, characterize quantities of interest for each pattern shape in the first cell, determine that the colors assigned in the first cell are all one to one mappable to the colors assigned in the second cells, characterize quantities of interest for each pattern shape in the second cell using the quantities of interest characterized for the first cell, and model the quantities of interest for the first cell and the second cell.

Abstract: Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor.

Abstract: Systems and methods for performing static timing analysis during IC design. A method is provided that includes obtaining canonical input data. The method further includes calculating at least one input condition identifier based on the canonical input data. The method further includes comparing the at least one input condition identifier to a table of values. The method further includes that when a match exists between the at least one input condition identifier and at least one value within the table of values, retrieving previously calculated timing data associated with the at least one value, and applying the previously calculated timing data in a timing model for a design under timing analysis.

Abstract: Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a color to each pattern shape in a first cell, assign a color to each pattern shape in a second cell, characterize quantities of interest for each pattern shape in the first cell, determine that the colors assigned in the first cell are all one to one mappable to the colors assigned in the second cells, characterize quantities of interest for each pattern shape in the second cell using the quantities of interest characterized for the first cell, and model the quantities of interest for the first cell and the second cell.

Abstract: Systems and methods for performing static timing analysis during IC design. A method is provided that includes obtaining canonical input data. The method further includes calculating at least one input condition identifier based on the canonical input data. The method further includes comparing the at least one input condition identifier to a table of values. The method further includes that when a match exists between the at least one input condition identifier and at least one value within the table of values, retrieving previously calculated timing data associated with the at least one value, and applying the previously calculated timing data in a timing model for a design under timing analysis.

Abstract: Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor.

Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.