Abstract: A method for performing a parallel static timing analysis in which multiple processes independently update a timing graph without requiring communication through a central coordinator module. Local processing queues are used to reduce locking overhead without causing excessive load imbalance. A parallel analysis is conducted on a circuit design represented by a timing graph formed by a plurality of interconnected nodes, the method including: using a computer for creating a shared work queue of ready to process independent nodes; assigning the independent nodes from the work queue to at least two parallel computation processes, simultaneously performing node analysis computations thereof; and modifying the circuit design by updating values of the processed independent nodes obtained from the node analysis, the at least two parallel computation processes independently updating the shared work queue to process a new plurality of independent nodes.

Abstract: Determining static timing analysis margin on non-controlling inputs of clock shaping and other digital circuits using reverse merge timing includes: selecting one or more circuits within the logic design having a plurality of inputs and using reverse merge; identifying a controlling input of the selected circuit from among this plurality of inputs; and determining for at least one non-controlling input of the circuit, a timing value that may be used to drive design optimization based on the difference between arrival times of the controlling and non-controlling inputs.

Abstract: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation.

Abstract: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation.

Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.

Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.

Abstract: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation.

Abstract: Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor.

Abstract: Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor.

Abstract: A method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times, comprising the steps of using a computer, identifying one or more pairs of asserted arrival times for which one or more correlations exist; propagating to each of the one or more pairs of asserted arrival times a timing value dependent on the one or more correlations; and performing a subsequent common path pessimism removal analysis for at least one test during which a timing value dependent on the one or more correlations between asserted arrival times is used to compute an adjusted test slack.

Abstract: A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load CCC for a transition or state of a driving CCC for which a load condition is being determined; a trace system that traverses paths in the load CCC from a set of input terminals; and an element replacement system that replaces circuit elements in the load CCC to create a modeled CCC, wherein a circuit element replacement is based on a type of circuit element encountered along a trace, and state and transition functions of nets connected to an encountered circuit element.

Abstract: A method for constructing delay rules which include the effects of MIS simulations for static timing analysis with reduced cost. The present method includes constructing skew windows for applying MIS penalties purely from SIS data, and scales the MIS penalties during rule use based upon how closely the skews in the use case approach the edge of the skew window. The method applies both to timing rule construction for a library of circuits and to timing rule construction for macros where only part of the circuits in the macro may be sensitive to skew between macro inputs.

Abstract: Methods for modeling a random variable with spatially inhomogenous statistical correlation versus distance, standard deviation, and mean by spatial interpolation with statistical corrections. The method includes assigning statistically independent random variable to a set of seed points in a coordinate frame and defining a plurality of test points at respective spatial locations in the coordinate frame. A equation for a random variable is determined for each of the test points by spatial interpolation from one or more of the random variable assigned to the seed points. The method further includes adjusting the equation of the random variable at each of the test point with respective correction factor equations.

Abstract: A method for efficient multithreaded analysis of a timing graph is described. The method is applicable to multithreaded common path pessimism removal, critical path traversing for timing report generation, and other types of analysis requiring traversal of sub-graphs of timing graph. In order to achieve high efficiency and scalability for parallel multithreaded execution, the number of access locks is minimized. One parent computation thread and multiple child threads are employed. The parent computational thread identifies the tasks for analysis and distributes them among child threads. Each child thread identifies a sub-graph to be analyzed, creates a thread-specific replica of the identified sub-graph, and performs the analysis required. After completing the analysis, the child thread transfers the results back to the main timing graph and waits for next task.

Abstract: Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor.

Abstract: A method for efficient multithreaded analysis of a timing graph is described. The method is applicable to multithreaded common path pessimism removal, critical path traversing for timing report generation, and other types of analysis requiring traversal of sub-graphs of timing graph. In order to achieve high efficiency and scalability for parallel multithreaded execution, the number of access locks is minimized. One parent computation thread and multiple child threads are employed. The parent computational thread identifies the tasks for analysis and distributes them among child threads. Each child thread identifies a sub-graph to be analyzed, creates a thread-specific replica of the identified sub-graph, and performs the analysis required. After completing the analysis, the child thread transfers the results back to the main timing graph and waits for next task.

Abstract: A method for performing a parallel static timing analysis in which multiple processes independently update a timing graph without requiring communication through a central coordinator module. Local processing queues are used to reduce locking overhead without causing excessive load imbalance. A parallel analysis is conducted on a circuit design represented by a timing graph formed by a plurality of interconnected nodes, the method including: using a computer for creating a shared work queue of ready to process independent nodes; assigning the independent nodes from the work queue to at least two parallel computation processes, simultaneously performing node analysis computations thereof; and modifying the circuit design by updating values of the processed independent nodes obtained from the node analysis, the at least two parallel computation processes independently updating the shared work queue to process a new plurality of independent nodes.

Abstract: A method for constructing delay rules which include the effects of MIS simulations for static timing analysis with reduced cost. The present method includes constructing skew windows for applying MIS penalties purely from SIS data, and scales the MIS penalties during rule use based upon how closely the skews in the use case approach the edge of the skew window. The method applies both to timing rule construction for a library of circuits and to timing rule construction for macros where only part of the circuits in the macro may be sensitive to skew between macro inputs.

Abstract: Disclosed are embodiments of a system and of an associated method for estimating the leakage current of an electronic circuit. The embodiments analyze a layout of an electronic circuit in order to identify all driven and non-driven nets within the electronic circuit, to identify all of the driven net-bounded partitions within the electronic circuit (based on the driven and non-driven nets), and to identify, for each driven net-bounded partition, all possible states of the electronic circuit that can leak. Then, using this information, the embodiments estimate the leakage current of the electronic circuit. This is accomplished by first determining, for each state of each driven net-bounded partition, a leakage current of the driven net-bounded partition and a probability that the state will occur in the driven net-bounded partition during operation of the electronic circuit.

Abstract: Determining static timing analysis margin on non-controlling inputs of clock shaping and other digital circuits using reverse merge timing includes: selecting one or more circuits within the logic design having a plurality of inputs and using reverse merge; identifying a controlling input of the selected circuit from among this plurality of inputs; and determining for at least one non-controlling input of the circuit, a timing value that may be used to drive design optimization based on the difference between arrival times of the controlling and non-controlling inputs.