Abstract: A semiconductor dynamic read/write memory device contains an array of rows and columns of one-transistor memory cells, with a differential sense amplifier for each column of cells. The sense amplifier has a pair of balanced bit lines extending from its inputs, in a quasi-folded bit line configuration. The memory cells are not directly connected to the bit lines, but instead are coupled to bit line segments. The row address selects a cell to be connected to a segment, and also selects one of the two segments to be connected to one of the two bit lines. Instead of being interleaved one-for-one, the word lines for cells to be connected to the two bit lines are in groups one group for each segment line; the groups are interleaved. The combined segment line and bit line capacitance has a more favorable ratio to the storage capacitance, compared to the one-for-one interleaved layout.

Abstract: A dynamic random access memory cell has a storage capacitor and an access transistor formed on only one sidewall of a trench etched into the face of a semiconductor bar. The storage capacitor uses the sidewall of the trench as the storage node, and uses a polysilicon plug as a common node. This polysilicon plug is part of a plate that extends along the face in the trench for a column of like cells, functioning to provide field-plate type of isolation between capacitors along the trench. The channel of the access transistor is formed in the upper part of the one sidewall of the trench, using an upper edge of the capacitor storage node as the source region of the transistor and having a buried N+ drain region on the face at the top. The capacitor areas are isolated from one another on opposite sidewalls, so an array can be laid out that has two cells per bit, to provide improved alpha particle immunity, or by using two wordlines per row a true crosspoint array is possible, providing higher density.

Abstract: A semiconductor dynamic read/write memory device contains an array of rows and columns of one-transistor memory cells, with a differential sense amplifier for each column of cells. The sense amplifier has a pair of balanced bit lines extending from its inputs, in a quasi-folded bit line configuration. The memory cells are not directly connected to the bit lines, but instead are coupled to bit line segments. The row address selects a cell to be connected to a segment, and also selects one of the two segments to be connected to one of the two bit lines. Instead of being interleaved one-for-one, the word lines for cells to be connected to the two bit lines are in groups one group for each segment line; the groups are interleaved. The combined segment line and bit line capacitance has a more favorable ratio to the storage capacitance, compared to the one-for-one interleaved layout.

Abstract: Adjustment of operating parameters for a functional circuit is provided by fuse links (44) and (45). For a DRAM, the fuse links (44) control the various internal delays of a timing control generator (40) and fuse links (45) control the sensitivity of sense amplifiers by controlling an access control circuit (42). The sense amplifiers (14) determine the access parameters for a plurality of memory cell arrays (10) and (12). By varying the parameters of the sense amplifiers, the access parameters can be controlled by one adjustment on the central control circuitry.

Abstract: A semiconductor dynamic read/write memory device contains an array of rows and columns of one-transistor memory cells, with a differential sense amplifier for each column of cells. The sense amplifier has a pair of balanced bit lines extending from its inputs, in a folded bit line configuration. The memory cells are not directly connected to the bit lines, but instead are coupled to bit line segments. The row address selects a cell to be connected to a segment, and also selects a segment to be connected to the bit line. The ratio of storage capacitance to effective bit line capacitance is increased, because the bit line itself is of lower capacitance to the substrate.

Abstract: A sense amplifier circuit for a CMOS DRAM or the like uses cross-coupled P-channel load transistors and cross-coupled N-channel driver transistors. Both of the P-channel transistors are in an N-well in the center of a symmetrical layout on the chip. Each N-channel transistor is split into two separate transistors, one on each side of the N-well, so that a balanced configuration is possible.

Abstract: A semiconductor memory device having an array of rows and columns of dynamic one-transistor memory cells uses a single-ended differential sense amplifier connected to each whole column line, rather than separately to column line halves. A bistable circuit with cross-coupled driver transistors has one side connected to the column line by a first coupling transistor which turns off as the row line goes high to trap a fixed reference voltage, then the other side is connected to the column line by a second coupling transistor which turns on after the column line has settled out. This column line voltage is related to whether a 1 or 0 is stored. The time needed to precharge the column line is short because two halves need not be precharged from different levels, and so the memory cycle time is short. Also, the device is less susceptible to errors due to alpha particles because a change of the bit line voltage equally effects both inputs to a sense amplifier.

Abstract: A block associative memory includes a plurality of memory cell arrays (70 and 72) arranged in rows and columns. Addressing of memory cells in the arrays (70 and 72) loads the data contained in one row thereof into a row of sense amplifiers (74). The selected row constitutes a block of memory. The data in the accessed block is compared with key data from a key data generator (20) in an equalizer circuit (90). The data in a given row or block is arranged in word groups. Each word group is compared with the key data and a match output generated for each data word group matching the key data word group. This match is decoded to output the column location of that word. The steps of retrieving the block from memory and associating the block with the key search data is performed in a single step and then additional blocks are selected for association with the key data word.

Abstract: A dynamic read/write memory cell of the one transistor type is made by a single-level polysilicon process in which the word lines and the gates of the access transistors are formed by the metal strips. No metal-to-silicon or metal-to-polysilicon contacts are needed. The access transistors are made by etching through polysilicon strips which are the capacitor bias plates. The size of the transistor is not determined by alignment accuracy.

Abstract: A programmable device is provided by a thin-oxide avalanche fuse element which is programmed at a voltage below the oxide breakdown level. This device may be used to fix the addresses of faulty rows or columns in a memory having redundant or substitute cells. Upon breakdown, the thin oxide is perforated by small holes which fill with silicon to create short circuit. The source or emitter of the transistor device may be separated from the drain and gate by thick filled oxide.

Abstract: A programmable device is provided by a thin-oxide avalanche fuse element which is programmed at a voltage below the oxide breakdown level. This device may be used in a memory array of the PROM type. Upon breakdown, the thin oxide is perforated by small holes which fill with silicon to create short circuit.

Abstract: A programmable device is provided by a thin-oxide avalanche fuse element which is programmed at a voltage below the oxide breakdown level. This device may be used to fix the addresses of faulty rows or columns in a memory having redundant or substitute cells. Upon breakdown, the thin oxide is perforated by small holes which fill with silicon to create short circuit.

Abstract: An improved electrically erasable semiconductor memory device of the N-channel, MOS, double level poly, programmable, read only memory or EPROM type is provided. The device is an array of cells electrically erased and programmed by dual injection into floating gates which are interposed between the channels and control gates. The electrical erasure or programming of the cells is accomplished by applying selected voltages to the source, drain, control gate and substrate to produce injection of electrons or holes.

Abstract: An improved method of making a semiconductor device such as an N-channel, double level poly, MOS read only memory or ROM array is provided; the array is of very dense structure and may be electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by polycrystalline silicon or metal row address lines. The electrical programming of the cells is accomplished by applying selected voltages to the source, drain, control gate and substrate. The very dense array results from a simplified manufacturing process generally compatible with standard N-channel silicon gate technology. Parallel strips of gate oxide, polycrystalline silicon, and nitride (functioning as an oxidation mask) are created in one mask step before field oxide is grown, then a perpendicular pattern of conductive strips is etched using a second mask step.

Abstract: A programmable device is provided by a thin-oxide avalanche fuse element which is programmed at a voltage below the oxide breakdown level. This device may be used to fix the addresses of faulty rows or columns in a memory having redundant or substitute cells. Upon breakdown, the thin oxide is perforated by small holes which fill with silicon to create short circuits. The source or emitter of the transistor device may be separated from the drain and gate by thick field oxide.

Abstract: Semiconductor devices are made by a process in which impurity is introduced, by ion implant, for example, after electrode layers are in place so that inaccuracies in alignment of masks or patterns are compensated. The implanted impurity changes the electrical characteristics of portions of the semiconductor device affected by the registration inaccuracies whereby malfunctions in the completed devices are prevented.

Abstract: A dynamic read/write memory cell of the one transistor type is made by a single-level polysilicon process in which the word lines and the gates of the access transistors are formed by the metal strips. No metal-to-silicon or metal-to-polysilicon contacts are needed. The access transistors are made by etching through polysilicon strips which are the capacitor bias plates. The size of the transistor is not determined by alignment accuracy.

Abstract: A memory system for a digital processor device having a 16-bit bidirectional bus with multiplexed addresses and data employs separate memory devices for the high order and low order data bytes. When less than 64K words of memory are used, there are unused address lines in the bus. A microcomputer may use memory devices partitioned 4K.times.8, needing 12 address pins. Both devices are constructed the same, but one accesses the low order byte and the other the high order byte under control of a single byte-select terminal. Mapping of the bus to memory device connections and internal connection of unused pins to address inputs or data input/output lines within the memory devices, along with the byte-select function, allow a single type of device to function in either position.

Abstract: Integrated circuit resistor elements which may be used as load devices in static MOS RAM cells are created vertically in polycrystalline silicon ion implanted to provide the desired resistivity. The method of making these devices is compatible with a standard self-aligned N-channel silicon-gate process. The cell size is reduced as the resistors can overly other elements, and an efficient layout provides a very small cell area.

Abstract: A fault tolerant memory device includes an array of rows and columns of dynamic random access memory cells and a set of EPROM cells of the floating gate type laid out with the same pitch, one aligned with each row, to store the identity of rows having bad cells. The EPROM cells are formed in preferred manner which permits them to be made with a standard N-channel process, and allows the row lines of the RAM and control gate connections to the EPROM cells to be of the same spacing.