Abstract: An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by two address lines. The cells may be electrically erased by applying selected voltages to the source, drain, control gate and substrate; the floating gate discharges through the insulator between the floating gate and the control gate, i.e., between first and second level polysilicon. An enhancement mode transistor in series with the floating gate device in each cell provides an improved voltage window for deprogramming.

Abstract: An electronic calculator with a power supply ON-OFF arrangement actuated by momentary-closure push-button switches which are part of the keyboard. A bistable latch circuit on the calculator chip is continuously powered by the battery, and is caused to flip to an ON condition by actuating an ON key, and this turns on a large, low-resistance transistor which is in series with the voltage supply line going to all of the other electronic circuitry on the chip.

Abstract: A cell for a semiconductor memory of the static type employs two conventional MOS transistors along with a field implanted resistance which functions as a grounded-gate junction FET. Along with other resistor elements, these devices provide a grounded-gate amplifier with voltage gain and a source follower, creating a circuit which is stable with either a "1" or "0" stored. No clock or other refresh circuitry is needed.

Abstract: An electronic calculator with a power supply ON-OFF arrangement actuated by momentary-closure push-button switches which are part of the keyboard. A bistable latch circuit on the calculator chip is continuously powered by the battery, and is caused to flip to an ON condition by actuating an ON key, and this turns on an oscillator, the output of which is pumped up to a level above the battery, and the high level voltage is used to drive a large, low-resistance transistor. This transistor is in series with the voltage supply line going to all of the other electronic circuitry on the chip. The oscillator and pump circuit assure that the drop across the transistor is negligible.

Abstract: A self-refresh MOS RAM cell uses a resistor element made by an ion implant step compatable with a self-aligned N-channel silicon-gate process. The resistor element is beneath the field oxide in the finished device, although the implant step is prior to formation of the thick oxide. The cell employs two transistors and a gated capacitor, connected in a manner such that a stored "1" switches the implanted resistor to a high impedance state, while a stored "0" maintains the resistor in a relatively low resistance state.

Abstract: A multiplexed system for displaying characters as in an electronic calculator, wherein the display is of the segemented type, typically employing visible light emitting diodes. Instead of actuating the digits or characters of the display in sequence while selectively actuating the segments of the display, the segments are scanned in a regular sequence while the digits are selectively actuated in a code corresponding to the data to be displayed. This system permits the construction of a calculator in which the display is driven directly from an MOS/LSI calculator chip without using digit and segment drivers.

Abstract: An integrated injection logic memory cell includes a latch circuit for holding a binary bit of information. Circuits are provided to maintain current injection into the latch circuit at all times, including during the reading and writing operations. The latch circuit is made up of a pair of cross coupled vertical, inverted transistors. The circuits for maintaining the injection current into the latch are made up of lateral transistors selectivity coupled to a memory access control circuit for supplying bi-level signals through word and column select lines.