Abstract: An n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits negative differential resistance in its output characteristic (drain current as a function of drain voltage) is disclosed. For a fixed gate voltage, the MISFET channel current, which flows between the drain and source terminals of the transistor, firstly increases as the drain-to-source voltage increases above zero Volts. Once the drain-to-source voltage reaches a pre-determined level, the current subsequently decreases with increasing drain-to-source voltage. In this region of operation, the device exhibits negative differential resistance, as the drain current decreases with increasing drain voltage. The drain-to-source voltage corresponding to the onset of negative differential resistance is also tunable. In addition, the drain current and negative differential resistance can be electronically tailored by adjusting the gate voltage.

Abstract: A charge trapping structure for use with an n-channel metal-insulator-semiconductor field-effect transistor (MISFET) is disclosed. A dielectric layer is formed close to a channel region of the MISFET, and includes a number of trapping sites which are arranged and have a concentration sufficient to temporarily store energetic electrons induced by an electric field to move from the channel into the trapping sites. The trapped electrons set up a counter field that depletes the channel of carriers, and as a bias voltage across the channel increases, the device exhibits negative differential resistance (NDR). The charge trapping structure, as well as the rest of the device, are formed using conventional CMOS processing techniques.

Abstract: A transistor device suitable for high voltage and low voltage applications, while maintaining minimum channel lengths. In one embodiment, pocket implants (310) are formed in a minimum channel device causing a reverse channel effect. The reverse channel effect is optimized for the minimum channel length of the device. Field implants (120), enhancement implants (130), and wells (140) are all formed using a single mask.

Abstract: A method of fabricating CMOS devices suitable for high voltage and low voltage applications, while maintaining minimum channel lengths for the devices. In one embodiment, pocket implants (310) are formed in a minimum channel device causing a reverse channel effect. The reverse channel effect is optimized for the minimum channel length of the device. Field implants (120), enhancement implants (130), and wells (140) are all formed using a single mask.

Abstract: A circuit and method for achieving an improved pre-programming of flash memory cells is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for hot electron pre-programming operations. By eliminating the need to pre-program the memory array with hot electrons, the invention provides a signicant improvement for flash arrays, because device life and reliability is extended. In addition, pre-programming time and power is reduced significantly since the operation takes place on a sector (parallel) basis rather than a single bit line (serial) basis, and a charge pump is not needed to generate the current injected into floating gates of cells in the sector.

Abstract: A novel erase mechanism using junction hot hole injection is disclosed for flash memory cell sector and bulk erase operations. A constant current supply is used so that a suitable junction voltage breakdown can be provided despite expected variations in cell structures, operations, etc. The inventive method eliminates the need for dual polarity voltage supplies for erase operations, and provides a method to achieve a tight distribution of erased cell threshold voltages. In addition, over-erasure problems associated with Fowler-Nordheim tunneling are essentially eliminated.

Abstract: A method for sensing the content of a FLASH memory cell, and a new FLASH memory cell structure that is suitable for use with this new sensing scheme. In a first aspect, a semiconductor memory cell comprises a lightly doped n-region including a channel region; a first insulating layer overlying portions of said n-region; a floating gate overlying said first insulating layer; a second insulating layer overlying said floating gate; and a control gate overlying second insulating layer.

Abstract: A circuit and method for achieving compressed distributions of erased cell threshold voltages in an EEPROM array is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for pre-programming operations before a bulk erase can take place. By eliminating the need to pre-program the memory array before each erasure, the process provides a signicant improvement for low power applications, because battery life is extended and write cycle time is enhanced.

Abstract: A method for maintaining a high field threshold voltage in a plurality of transistors of reduced size in a periphery region of a Flash EPROM semiconductor circuit includes forming a first polysilicon layer as a floating poly in a predetermined number of transistors of the plurality of transistors in the periphery region, and forming a second polysilicon layer as a common gate line in the plurality of transistors, wherein the predetermined number of transistors prevent breakdown of the plurality of transistors below a predetermined field threshold voltage. In one aspect, the field oxide layer has a thickness of about 2500 angstroms.

Abstract: A circuit and method for achieving compressed distributions of erased cell threshold voltages in an EEPROM array is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for pre-programming operations before a bulk erase can take place. By eliminating the need to pre-program the memory array before each erasure, the process provides a signicant improvement for low power applications, because battery life is extended and write cycle time is enhanced.

Abstract: A test circuit for observing charge retention characteristics of cells in a flash memory array is disclosed. Unlike prior art structures, the present circuit monitors both charge loss and charge gain of cells in the array. In this way, cells having conduction thresholds below a desired target threshold and cells having conduction thresholds above a desired target threshold can both be observed. The circuit includes a regular memory array, and a mirror array formed with devices having opposite channel types to the regular array. By identifying and evaluating more accurately the threshold characteristics of a particular cell design or cell process, improvements can be made to such designs and processes in a more rapid and optimal fashion.

Abstract: A plurality of transistors according to the present invention formed on a semiconductor wafer including a plurality of non-ESD transistors, the plurality of non-ESD transistors including spacer regions and impurity implant regions encroaching the spacer regions, and a plurality of ESD transistors, the plurality of ESD transistors formed at a predetermined angular offset from the non-ESD transistors. Further, the plurality of ESD transistors include the spacer regions and impurity implant regions encroaching the spacer regions further than the impurity implant regions of the non-ESD transistors.

Abstract: The present invention is directed toward a novel type of FLASH EEPROM cell that is highly scalable in size, easy to fabricate, reliable and capable of in-system programmability. The semiconductor memory cell comprises a lightly doped n- region including a channel region, a first insulating layer overlying portions of said n- region, and a floating gate overlying said first insulating layer. The cell further includes a second insulating layer overlying said floating gate and a control gate overlying second insulating layer.

Abstract: A method for sensing the content of a FLASH memory cell, and a new FLASH memory cell structure that is suitable for use with this new sensing scheme. In a first aspect, a semiconductor memory cell comprises a lightly doped n-region including a channel region; a first insulating layer overlying portions of said n-region; a floating gate overlying said first insulating layer; a second insulating layer overlying said floating gate; and a control gate overlying second insulating layer.

Abstract: A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.

Abstract: In one aspect of the present invention, a method includes the steps of providing a first test cell electrically isolated from the substrate, unexposed to the SAS etch and having a first core profile. The method further includes providing a second test cell electrically isolated from the substrate, exposed to the SAS etch, and having a second core profile. Additionally, the method includes performing the SAS etch, measuring electrical characteristics of the first and second cells, and comparing the measured electrical characteristics to determine an amount of gouging. In a further aspect of the present invention, a method includes the steps of forming a pair of test structures in electrical isolation of a substrate of the cell, and measuring resistance values for each of the pair of test structures to determine the amount of gouging. In addition, the method includes protecting one of the pair of test structures from the SAS etch.

Abstract: A method for reducing encroachment of an impurity implant into a channel region in a non-ESD transistor in a semiconductor circuit, the non-ESD transistor receiving both first and second implant dopants, and the circuit including a plurality of ESD transistors includes forming the ESD transistors of the circuit at a predetermined angular offset from the non-ESD transistor, and performing the second dopant implant at a predetermined tilt implant angle, wherein the non-ESD transistor has reduced encroachment of the impurity implant. A plurality of transistors formed on a semiconductor wafer include a plurality of non-ESD transistors, the plurality of non-ESD transistors including spacer regions and impurity implant regions encroaching the spacer regions, and a plurality of ESD transistors, the plurality of ESD transistors formed at a predetermined angular offset from the non-ESD transistors.

Abstract: A method and system for providing a semiconductor device with device isolation and leakage current control which entails processing a semiconductor substrate to form a semiconductor circuit, and providing at least one high energy implant on the semiconductor circuit is disclosed. The high energy implant is provided at an angle to source and drain regions of the semiconductor circuit so as to allow a dosage from the at least one high energy implant below and away from the surface of the active device region. In so doing, a profile is provided in which dopant distribution is substantially uniform. Therefore, the breakdown characteristics are increased and the junction capacitance of the device is reduced. Accordingly, a device manufactured in accordance with the present invention has significant advantages over devices manufactured in accordance with conventional processes.

Abstract: This antifuse includes: a sublithographic conductive pattern (18); an antifuse material (24) overlying said sublithographic conductive pattern (18); and a conductive layer (26) overlying the antifuse material (24) to form a reduced area antifuse (10). Other devices, systems and methods are also disclosed.

Abstract: The present invention presents methods for reducing the discharge time of a Flash EPROM cell. In one aspect, a method includes the steps of forcing an ultraviolet voltage threshold, UVV.sub.t, below a discharge threshold voltage, V.sub.t. The method further comprises reducing the UVV.sub.t to about 0 V. Further, the method further comprises the step of reducing a core cell implant of a p-type dopant into a substrate of the cell. In a further aspect, a method for decreasing the discharge time includes the steps of providing a core cell implant of a p-type dopant into a surface of a substrate of the cell, and providing a surface doping of an n-type dopant into the core of the substrate, where the core implant reduces punchthrough and the surface doping of an n-type dopant reduces V.sub.t in the cell.