Abstract: Disclosed herein is a channel hot-carrier page write including an array of stacked gate flash EEPROM memory cells operating in a very low energy programming mode permitting page writing of 1024 bits within a 20-100 .mu.S programming interval. Internal programming voltage levels are derived from on-chip circuits, such as charge pumps, operated from a single +V.sub.CC source. In a preferred embodiment, a cache memory buffers data transfers between a computer bus and the page oriented storage array. In another embodiment, core doping is increased in the channel and drain regions to enhance hot carrier injection and to lower the programming drain voltage. The stacked floating gate structure is shown to exhibit a high programming efficiency in a range from 10.sup.-6 to 10.sup.-4 at drain voltages below 5.2 VDC. In another embodiment AC components of the programming current are minimized by precharging a common source line at the start of a programming cycle.

Abstract: A buried layer which is highly doped and implanted with high energy in a lightly doped isolated well in which an array of flash EPROM cells are provided. The buried layer is doped with the same conductivity dopant as the well in which it is provided, for example a p.sup.+ -type buried implant is provided in a p-type well. The buried layer enables channel size of the flash EPROM cells to be reduced providing a higher array density. Channels of the flash EPROM cells are reduced because the buried layer provides a low resistance path between channels of the flash EPROM cells enabling erase to be performed by applying a voltage potential difference between the gate and substrate of a cell.

Abstract: A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.

Abstract: A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.

Abstract: A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.

Abstract: In one described embodiment of the present invention, a method for manufacturing a sublithographic semiconductor feature is disclosed. This method comprises: depositing a feature material on a substrate (14); depositing and patterning a resist material (20) over said feature material; vertically, anisotropically etching said feature material to form a feature pattern (18) with substantially vertical sidewalls underlying said resist material pattern (20); isotropically etching said feature pattern (18) such that said feature pattern (18) sidewalls are undercut from beneath said resist material pattern (20) to form a reduced geometry feature (18) whereby said reduced geometry feature (18) has a geometry less than that of the overlying resist material pattern (20). Another described embodiment comprises an antifuse formed by the above method wherein the antifuse dielectric (24) is a nitride-oxide (N-O) layer.