Patents by Inventor David L. Questad
David L. Questad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10750615Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.Type: GrantFiled: May 28, 2019Date of Patent: August 18, 2020Assignee: International Business Machines CorporationInventors: Michael A. Gaynes, Jeffrey D. Gelorme, Robert P. Kuder, II, Daniel J. Littrell, Thomas E. Lombardi, Marie-Claude Paquet, Frank L. Pompeo, David L. Questad, James Speidell, Sri M. Sri-Jayantha, Son K. Tran
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Patent number: 10699972Abstract: A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.Type: GrantFiled: November 30, 2017Date of Patent: June 30, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William E. Bernier, Timothy H. Daubenspeck, Virendra R. Jadhav, Valerie A. Oberson, David L. Questad
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Publication number: 20190281702Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.Type: ApplicationFiled: May 28, 2019Publication date: September 12, 2019Inventors: Michael A. Gaynes, Jeffrey D. Gelorme, Robert P. Kuder, II, Daniel J. Littrell, Thomas E. Lombardi, Marie-Claude Paquet, Frank L. Pompeo, David L. Questad, James Speidell, Sri M. Sri-Jayantha, Son K. Tran
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Patent number: 10381276Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.Type: GrantFiled: December 17, 2015Date of Patent: August 13, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sushumna Iruvanti, Shidong Li, Marek A. Orlowski, David L. Questad, Tuhin Sinha, Krishna R. Tunga, Thomas A. Wassick, Randall J. Werner, Jeffrey A. Zitz
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Patent number: 10368441Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.Type: GrantFiled: March 22, 2018Date of Patent: July 30, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael A. Gaynes, Jeffrey D. Gelorme, Robert P. Kuder, II, Daniel J. Littrell, Thomas E. Lombardi, Marie-Claude Paquet, Frank L. Pompeo, David L. Questad, James Speidell, Sri M. Sri-Jayantha, Son K. Tran
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Patent number: 10342160Abstract: Structures and methods for providing heat sink attachments on existing heat sinks. According to a device, a first heat sink comprises a first base and fins extending from the first base. The first base comprises a cutout therein and a first base bottom surface contacting a first electronic component. A second heat sink comprises a second base and fins extending from the second base. The second heat sink is located in the cutout of the first heat sink. The second base comprises a second base bottom surface contacting a second electronic component. A pressure plate is attached to the first heat sink and overlays the second heat sink. The pressure plate contacts the second heat sink and applies pressure between the second heat sink and the second electronic component.Type: GrantFiled: November 3, 2017Date of Patent: July 2, 2019Assignee: International Business Machines CorporationInventors: Louis-Marie Achard, Kenneth C. Marston, Janak G. Patel, David L. Questad
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Patent number: 10249548Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.Type: GrantFiled: November 15, 2017Date of Patent: April 2, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sushumna Iruvanti, Shidong Li, Marek A. Orlowski, David L. Questad, Tuhin Sinha, Krishna R. Tunga, Thomas A. Wassick, Randall J. Werner, Jeffrey A. Zitz
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Publication number: 20180213645Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.Type: ApplicationFiled: March 22, 2018Publication date: July 26, 2018Inventors: Michael A. Gaynes, Jeffrey D. Gelorme, Robert P. Kuder, II, Daniel J. Littrell, Thomas E. Lombardi, Marie-Claude Paquet, Frank L. Pompeo, David L. Questad, James Speidell, Sri M. Sri-Jayantha, Son K. Tran
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Patent number: 10014273Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.Type: GrantFiled: July 21, 2016Date of Patent: July 3, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas E. Lombardi, Donald Merte, Gregg B. Monjeau, David L. Questad, Son K. Tran
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Patent number: 9974179Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.Type: GrantFiled: March 22, 2017Date of Patent: May 15, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael A. Gaynes, Jeffrey D. Gelorme, Robert P. Kuder, II, Daniel J. Littrell, Thomas E. Lombardi, Marie-Claude Paquet, Frank L. Pompeo, David L. Questad, James Speidell, Sri M. Sri-Jayantha, Son K. Tran
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Publication number: 20180082912Abstract: A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.Type: ApplicationFiled: November 30, 2017Publication date: March 22, 2018Inventors: William E. Bernier, Timothy H. Daubenspeck, Virendra R. Jadhav, Valerie A. Oberson, David L. Questad
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Publication number: 20180076101Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.Type: ApplicationFiled: November 15, 2017Publication date: March 15, 2018Inventors: Sushumna Iruvanti, Shidong Li, Marek A. Orlowski, David L. Questad, Tuhin Sinha, Krishna R. Tunga, Thomas A. Wassick, Randall J. Werner, Jeffrey A. Zitz
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Publication number: 20180054915Abstract: Structures and methods for providing heat sink attachments on existing heat sinks. According to a device, a first heat sink comprises a first base and fins extending from the first base. The first base comprises a cutout therein and a first base bottom surface contacting a first electronic component. A second heat sink comprises a second base and fins extending from the second base. The second heat sink is located in the cutout of the first heat sink. The second base comprises a second base bottom surface contacting a second electronic component. A pressure plate is attached to the first heat sink and overlays the second heat sink. The pressure plate contacts the second heat sink and applies pressure between the second heat sink and the second electronic component.Type: ApplicationFiled: November 3, 2017Publication date: February 22, 2018Applicant: International Business Machines CorporationInventors: Louis-Marie Achard, Kenneth C. Marston, Janak G. Patel, David L. Questad
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Patent number: 9899279Abstract: A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.Type: GrantFiled: October 17, 2014Date of Patent: February 20, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William E. Bernier, Timothy H. Daubenspeck, Virendra R. Jadhav, Valerie A. Oberson, David L. Questad
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Patent number: 9883612Abstract: Structures and methods for providing heat sink attachments on existing heat sinks. According to a device, a first heat sink comprises a first base and fins extending from the first base. The first base comprises a cutout therein and a first base bottom surface contacting a first electronic component. A second heat sink comprises a second base and fins extending from the second base. The second heat sink is located in the cutout of the first heat sink. The second base comprises a second base bottom surface contacting a second electronic component. A pressure plate is attached to the first heat sink and overlays the second heat sink. The pressure plate contacts the second heat sink and applies pressure between the second heat sink and the second electronic component.Type: GrantFiled: June 2, 2015Date of Patent: January 30, 2018Assignee: International Business Machines CorporationInventors: Louis-Marie Achard, Kenneth C. Marston, Janak G. Patel, David L. Questad
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Publication number: 20170196089Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.Type: ApplicationFiled: March 22, 2017Publication date: July 6, 2017Inventors: Michael A. Gaynes, Jeffrey D. Gelorme, Robert P. Kuder, II, Daniel J. Littrell, Thomas E. Lombardi, Marie-Claude Paquet, Frank L. Pompeo, David L. Questad, James Speidell, Sri M. Sri-Jayantha, Son K. Tran
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Publication number: 20170178982Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.Type: ApplicationFiled: December 17, 2015Publication date: June 22, 2017Inventors: Sushumna Iruvanti, Shidong Li, Marek A. Orlowski, David L. Questad, Tuhin Sinha, Krishna R. Tunga, Thomas A. Wassick, Randall J. Werner, Jeffrey A. Zitz
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Patent number: 9627784Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.Type: GrantFiled: December 1, 2015Date of Patent: April 18, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael A. Gaynes, Jeffrey D. Gelorme, Robert P. Kuder, II, Daniel J. Littrell, Thomas E. Lombardi, Marie-Claude Paquet, Frank L. Pompeo, David L. Questad, James Speidell, Sri M. Sri-Jayantha, Son K. Tran
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Publication number: 20160360645Abstract: Structures and methods for providing heat sink attachments on existing heat sinks. According to a device, a first heat sink comprises a first base and fins extending from the first base. The first base comprises a cutout therein and a first base bottom surface contacting a first electronic component. A second heat sink comprises a second base and fins extending from the second base. The second heat sink is located in the cutout of the first heat sink. The second base comprises a second base bottom surface contacting a second electronic component. A pressure plate is attached to the first heat sink and overlays the second heat sink. The pressure plate contacts the second heat sink and applies pressure between the second heat sink and the second electronic component.Type: ApplicationFiled: June 2, 2015Publication date: December 8, 2016Inventors: Louis-Marie Achard, Kenneth C. Marston, Janak G. Patel, David L. Questad
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Publication number: 20160329297Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.Type: ApplicationFiled: July 21, 2016Publication date: November 10, 2016Inventors: Thomas E. LOMBARDI, Donald MERTE, Gregg B. MONJEAU, David L. QUESTAD, Son K. TRAN