Patents by Inventor David L. Questad
David L. Questad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8338286Abstract: A method for reducing stress on under ball metallurgy (UBM) is disclosed. A collar is disposed around the ball to provide support, and prevent solder interaction in the undercut areas of the UBM. In one embodiment, the collar is comprised of photosensitive polyimide.Type: GrantFiled: October 5, 2010Date of Patent: December 25, 2012Assignee: International Business Machines CorporationInventors: Eric David Perfecto, Harry David Cox, Timothy Harrison Daubenspeck, David L. Questad, Brian Richard Sundlof
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Publication number: 20120299195Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 ?m. The platted through hole landing includes an etched pattern and a copper top surface.Type: ApplicationFiled: August 8, 2012Publication date: November 29, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karan Kacker, Douglas O. Powell, David L. Questad, David J. Russell, Sri M. Sri-Jayantha
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Publication number: 20120286433Abstract: An electrical conductor is connected to a first microcircuit element having a first connector site axis and a second microcircuit having a second connector site axis. The first microcircuit and the second microcircuit are separated by and operatively associated with a first electrical insulator layer. The conductor and the first microcircuit element are separated by and operatively associated with a second electrical insulator layer. At least one of the first electrical insulator layer and the second electrical insulator layer comprise a polymeric material. The microcircuit includes a UBM and solder connection to a FBEOL via opening. Sufficiently separating the first connector site axis and the second connector site axis so they are not concentric, decouples the UBM and solder connection to the FBEOL via opening. This eliminates or minimizes electromigration and the white bump problems. A process comprises manufacturing the microcircuit.Type: ApplicationFiled: May 22, 2012Publication date: November 15, 2012Applicant: International Business Machines CorporationInventors: Minhua Lu, Eric D. Pefecto, David L. Questad, Sudipta K. Ray
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Publication number: 20120279061Abstract: A method of fabricating a substrate via structure in a substrate/chip assembly includes steps of: disposing a center via stack for electrical interconnects in the substrate/chip assembly; and providing a plurality of stacked vias surrounding the center via stack. The plurality of stacked vias encircle the center via stack, resulting in no isolated via stacks on the structure. The plurality of stacked vias have both functional and non-functional vias.Type: ApplicationFiled: July 14, 2012Publication date: November 8, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karan Kacker, Douglas O. Powell, David L. Questad, David J. Russell, Sri M. Sri-Jayantha
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Patent number: 8298929Abstract: Semiconductor structures, methods of manufacture and design structures are provided. The structure includes at least one offset crescent shaped solder via formed in contact with an underlying metal pad of a chip. The at least one offset crescent shaped via is offset with respect to at least one of the underlying metal pad and an underlying metal layer in direct electrical contact with an interconnect of the chip which is in electrical contact with the underlying metal layer.Type: GrantFiled: December 3, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Timothy H. Daubenspeck, Gary Lafontant, Ekta Misra, David L. Questad, George J. Scott, Krystyna W. Semkow, Timothy D. Sullivan, Thomas A. Wassick, Steven L. Wright
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Publication number: 20120267158Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes an etched pattern.Type: ApplicationFiled: July 1, 2012Publication date: October 25, 2012Applicant: International Business Machines CorporationInventors: Karan Kacker, Douglas O. Powell, David L. Questad, David J. Russell, Sri M. Sri-Jayantha
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Patent number: 8258410Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes a compliant center zone; and spring-like stiffness-reducing connectors for connecting the compliant center zone of the platted through hole landing.Type: GrantFiled: January 26, 2008Date of Patent: September 4, 2012Assignee: International Business Machines CorporationInventors: Karan Kacker, Douglas O. Powell, David L. Questad, David J. Russell, Sri M. Sri-Jayantha
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Patent number: 8242593Abstract: A substrate via structure for stacked vias in a substrate/chip assembly includes: a center via stack and a plurality of stacked vias clustered around the center via stack. In this structure, the center via and the surrounding vias are made of copper. Some of the surrounding vias may be non-functional vias and these may be of a different height than the functional vias.Type: GrantFiled: January 27, 2008Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: Karan Kacker, Douglas O. Powell, David L. Questad, David J. Russell, Sri M. Sri-Jayantha
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Publication number: 20120187180Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.Type: ApplicationFiled: March 16, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas E. LOMBARDI, Donald MERTE, Gregg B. MONJEAU, David L. QUESTAD, Son K. TRAN
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Patent number: 8227918Abstract: A microcircuit article of manufacture comprises an electrical conductor electrically connected to both a first microcircuit element at a site comprising a first connector site having a first connector site axis and a second microcircuit element at a site comprising a second connector site having a second connector site axis. The first microcircuit element and the second microcircuit element are separated by and operatively associated with a layer comprising a first electrical insulator, whereas the conductor and the first microcircuit element are separated by and operatively associated with a layer comprising a second electrical insulator. At least one of the first electrical insulator layer and the second electrical insulator layer comprise a polymeric electrical insulator. In another embodiment, both electrical insulator layers comprise polymeric insulator layers. The microcircuit includes a UBM and solder connection to a FBEOL via opening.Type: GrantFiled: September 16, 2009Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Minhua Lu, Eric D. Pefecto, David L. Questad, Sudipta K. Ray
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Patent number: 8198133Abstract: Controlled collapse chip connection (C4) structures and methods of manufacture, and more specifically to structures and methods to improve lead-free C4 interconnect reliability. A structure includes a ball limited metallization (BLM) layer and a controlled collapse chip connection (C4) solder ball formed on the BLM layer. Additionally, the structure includes a final metal pad layer beneath the BLM layer and a cap layer beneath the final metal pad layer. Furthermore, the structure includes an air gap formed beneath the C4 solder ball between the final metal pad layer and one of the BLM layer and the cap layer.Type: GrantFiled: July 13, 2009Date of Patent: June 12, 2012Assignee: International Business Machines CorporationInventors: Timothy H. Daubenspeck, Paul Fortier, Jeffrey P. Gambino, Christopher D. Muzzy, David L. Questad, Wolfgang Sauter, Timothy D. Sullivan
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Publication number: 20120139123Abstract: Semiconductor structures, methods of manufacture and design structures are provided. The structure includes at least one offset crescent shaped solder via formed in contact with an underlying metal pad of a chip. The at least one offset crescent shaped via is offset with respect to at least one of the underlying metal pad and an underlying metal layer in direct electrical contact with an interconnect of the chip which is in electrical contact with the underlying metal layer.Type: ApplicationFiled: December 3, 2010Publication date: June 7, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy H. Daubenspeck, Gary Lafontant, Ekta Misra, David L. Questad, George J. Scott, Krystyna W. Semkow, Timothy D. Sullivan, Thomas A. Wassick, Steven L. Wright
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Patent number: 8188597Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.Type: GrantFiled: September 22, 2010Date of Patent: May 29, 2012Assignee: International Business Machines CorporationInventors: Thomas E. Lombardi, Donald Merte, Gregg B. Monjeau, David L. Questad, Son K. Tran
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Publication number: 20120083114Abstract: A method for reducing stress on under ball metallurgy (UBM) is disclosed. A collar is disposed around the ball to provide support, and prevent solder interaction in the undercut areas of the UBM. In one embodiment, the collar is comprised of photosensitive polyimide.Type: ApplicationFiled: October 5, 2010Publication date: April 5, 2012Applicant: International Business Machines CorporationInventors: ERIC DANIEL PERFECTO, Harry David Cox, Timothy Harrison Daubenspeck, David L. Questad, Brian Richard Sundlof
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Publication number: 20120070940Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.Type: ApplicationFiled: September 22, 2010Publication date: March 22, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas E. Lombardi, Donald Merte, Gregg B. Monjeau, David L. Questad, Son K. Tran
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Patent number: 8037594Abstract: Disclosed are thermally conductive plates. Each plate is configured such that a uniform adhesive-filled gap may be achieved between the plate and a heat generating structure when the plate is bonded to the heat generating structure and subjected to a temperature within a predetermined temperature range that causes the heat generating structure to warp. Additionally, this disclosure presents the associated methods of forming the plates and of bonding the plates to a heat generating structure. In one embodiment the plate is curved and modeled to match the curved surface of a heat generating structure within the predetermined temperature range. In another embodiment the plate is a multi-layer conductive structure that is configured to undergo the same warpage under a thermal load as the heat generating structure. Thus, when the plate is bonded with the heat generating structure it is able to achieve and maintain a uniform adhesive-filled gap at any temperature.Type: GrantFiled: May 7, 2008Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: Jeffrey T. Coffin, Michael A. Gaynes, David L. Questad, Kamal K. Sikka, Hilton T. Toy, Jamil A. Wakil
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Publication number: 20110193218Abstract: A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.Type: ApplicationFiled: February 5, 2010Publication date: August 11, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles L. Arvin, Raschid J. Bezama, Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, David L. Questad, Wolfgang Sauter, Timothy D. Sullivan, Brian R. Sundlof
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Publication number: 20110063815Abstract: A microcircuit article of manufacture comprises an electrical conductor electrically connected to both a first microcircuit element at a site comprising a first connector site having a first connector site axis and a second microcircuit element at a site comprising a second connector site having a second connector site axis. The first microcircuit element and the second microcircuit element are separated by and operatively associated with a layer comprising a first electrical insulator, whereas the conductor and the first microcircuit element are separated by and operatively associated with a layer comprising a second electrical insulator. At least one of the first electrical insulator layer and the second electrical insulator layer comprise a polymeric electrical insulator. In another embodiment, both electrical insulator layers comprise polymeric insulator layers. The microcircuit includes a UBM and solder connection to a FBEOL via opening.Type: ApplicationFiled: September 16, 2009Publication date: March 17, 2011Applicant: International Business Machines CorporationInventors: Minhua Lu, Eric D. Perfecto, David L. Questad, Sudipta K. Ray
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Patent number: 7875502Abstract: A chip fabrication method. A provided structure includes: a transistor on a semiconductor substrate, N interconnect layers on the semiconductor substrate and the transistor (N>0), and a first dielectric layer on the N interconnect layers. The transistor is electrically coupled to the N interconnect layers. P crack stop regions and Q crack stop regions are formed on the first dielectric layer (P, Q>0). The first dielectric layer is sandwiched between the N interconnect layers and a second dielectric layer that is formed on the first dielectric layer. Each P crack stop region is completely surrounded by the first and second dielectric layers. The second dielectric layer is sandwiched between the first dielectric layer and an underfill layer that is formed on the second dielectric layer. Each Q crack stop region is completely surrounded by the first dielectric layer and the underfill layer.Type: GrantFiled: May 27, 2010Date of Patent: January 25, 2011Assignee: International Business Machines CorporationInventors: Peter J. Brofman, Jon Alfred Casey, Ian D. Melville, David L. Questad, Wolfgang Sauter, Thomas Anthony Wassick
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Publication number: 20110006422Abstract: Controlled collapse chip connection (C4) structures and methods of manufacture, and more specifically to structures and methods to improve lead-free C4 interconnect reliability. A structure includes a ball limited metallization (BLM) layer and a controlled collapse chip connection (C4) solder ball formed on the BLM layer. Additionally, the structure includes a final metal pad layer beneath the BLM layer and a cap layer beneath the final metal pad layer. Furthermore, the structure includes an air gap formed beneath the C4 solder ball between the final metal pad layer and one of the BLM layer and the cap layer.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, David L. Questad, Wolfgang Sauter, Timothy D. Sullivan