Abstract: Disclosed are thermally conductive plates. Each plate is configured such that a uniform adhesive-filled gap may be achieved between the plate and a heat generating structure when the plate is bonded to the heat generating structure and subjected to a temperature within a predetermined temperature range that causes the heat generating structure to warp. Additionally, this disclosure presents the associated methods of forming the plates and of bonding the plates to a heat generating structure. In one embodiment the plate is curved and modeled to match the curved surface of a heat generating structure within the predetermined temperature range. In another embodiment the plate is a multi-layer conductive structure that is configured to undergo the same warpage under a thermal load as the heat generating structure. Thus, when the plate is bonded with the heat generating structure it is able to achieve and maintain a uniform adhesive-filled gap at any temperature.

Abstract: The present invention provides a method of strengthening a structure, to heal the imperfection of the structure, to reinforce the structure, and thus strengthening the dielectric without compromising the desirable low dielectric constant of the structure. The inventive method includes the steps of providing a semiconductor structure having at least one interconnect structure; dicing the interconnect structure; applying at least one infiltrant into the interconnect structure; and infiltrating the infiltrant to infiltrate into the interconnect structure.

Abstract: Structures and a method for forming the same. The structure includes a semiconductor substrate, a transistor on the semiconductor substrate, and N interconnect layers on top of the semiconductor substrate, N being a positive integer. The transistor is electrically coupled to the N interconnect layers. The structure further includes a first dielectric layer on top of the N interconnect layers and P crack stop regions on top of the first dielectric layer, P being a positive integer. The structure further includes a second dielectric layer on top of the first dielectric layer. Each crack stop region of the P crack stop regions is completely surrounded by the first dielectric layer and the second dielectric layer. The structure further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer.

Abstract: A tensile strength testing structure for controlled collapse chip connections (C4) disposed above a substrate includes: a fixture base configured for positioning substrates with C4; a top fixture plate with through hole channels; test pins for insertion through the through hole channels; wherein dimensional tolerances of the substrates are accounted for with openings on at least two sides of the fixture base for positioning the substrates, and during alignment of the top fixture plate through hole channels with the C4 prior to securing the top fixture plate to the fixture base; wherein the test pins are strain hardened metal wires; wherein lower ends of the test pins are joined to the C4 during a solder reflow process; and wherein distal ends of the test pins are pulled in a direction perpendicular to the testing structure to determine the tensile strength of the C4.

Abstract: Disclosed are thermally conductive plates. Each plate is configured such that a uniform adhesive-filled gap may be achieved between the plate and a heat generating structure when the plate is bonded to the heat generating structure and subjected to a temperature within a predetermined temperature range that causes the heat generating structure to warp. Additionally, this disclosure presents the associated methods of forming the plates and of bonding the plates to a heat generating structure. In one embodiment the plate is curved and modeled to match the curved surface of a heat generating structure within the predetermined temperature range. In another embodiment the plate is a multi-layer conductive structure that is configured to undergo the same warpage under a thermal load as the heat generating structure. Thus, when the plate is bonded with the heat generating structure it is able to achieve and maintain a uniform adhesive-filled gap at any temperature.

Abstract: A semiconductor chip and methods for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.

Abstract: A design structure to provide a package for a semiconductor chip that minimizes the stresses and strains that arise from differential thermal expansion in chip to substrate or chip to card interconnections. An improved set of design structure vias above the final copper metallization level that mitigate shocks during semiconductor assembly and testing. Other embodiments include design structures having varying micro-mechanical support structures that further minimize stress and strain in the semiconductor package.

Abstract: A semiconductor package is disclosed including a first capture pad isolated from an adjacent second capture pad by an insulator; a first plurality of electrically active vias connecting the first capture pad to the second capture pad; a third capture pad isolated from the second capture pad by an insulator; and a second plurality of electrically active vias connecting the second capture pad to the third capture pad. Each via of the first plurality of active vias is non-aligned with each via of the second plurality of active vias. The structure provides reduction of strain on the vias when a shear force is applied to a ball grid array used therewith while minimizing the degradation of the electrical signals.

Abstract: Disclosed are thermally conductive plates. Each plate is configured such that a uniform adhesive-filled gap may be achieved between the plate and a heat generating structure when the plate is bonded to the heat generating structure and subjected to a temperature within a predetermined temperature range that causes the heat generating structure to warp. Additionally, this disclosure presents the associated methods of forming the plates and of bonding the plates to a heat generating structure. In one embodiment the plate is curved and modeled to match the curved surface of a heat generating structure within the predetermined temperature range. In another embodiment the plate is a multi-layer conductive structure that is configured to undergo the same warpage under a thermal load as the heat generating structure. Thus, when the plate is bonded with the heat generating structure it is able to achieve and maintain a uniform adhesive-filled gap at any temperature.

Abstract: A circuit board comprises a resin-filled plated (RFP) through-hole; a dielectric layer over the RFP through-hole; a substantially circular RFP cap in the dielectric layer and connected to an upper opening of the RFP through-hole; a via stack in the dielectric layer; and a plurality of via lands extending radially outward from the via stack, wherein each of the plurality of via lands is diametrically larger than the RFP cap. Preferably, the RFP cap comprises a diameter of at least 300 ?m. Preferably, each of the via lands comprises a substantially circular shape having a diameter of at least 400 ?m. Moreover, the circuit board further comprises a ball grid array pad connected to the via stack; and input/output ball grid array pads connected to the ball grid array pad. Additionally, the circuit board further comprises metal planes in the dielectric layer.

Abstract: A semiconductor structure and method for forming the same. The semiconductor structure includes (a) a substrate and (b) a chip which includes N chip solder balls, N is a positive integer, and the N chip solder balls are in electrical contact with the substrate. The semiconductor structure further includes (c) first, second, third, and fourth corner underfill regions which are respectively at first, second, third, and fourth corners of the chip, and sandwiched between the chip and the substrate. The semiconductor structure further includes (d) a main underfill region sandwiched between the chip and the substrate. The first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate. A corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill material of the main underfill region.

Abstract: A land grid array (LGA) assembly includes a chip carrier substrate having at least one chip attached thereto, and a stiffener member attached to the chip carrier substrate, the stiffener member further including a honeycomb material. A cap is attached to the chip and stiffener member.

Abstract: A mesh-like reinforcing structure to inhibit delamination and cracking is fabricated in a multilayer semiconductor device using low-k dielectric materials and copper-based metallurgy. The mesh-like interconnection structure comprises conductive pads interconnected by conductive lines at each wiring level with each pad conductively connected to its adjacent pad at the next wiring level by a plurality of conductive vias. The conductive pads, lines and vias are fabricated during the normal BEOL wiring level integration process. The reinforcing structure provides both vertical and horizontal reinforcement and may be fabricated on the periphery of the active device region or within open regions of the device that are susceptible to delamination and cracking.

Abstract: A mesh-like reinforcing structure to inhibit delamination and cracking is fabricated in a multilayer semiconductor device using low-k dielectric materials and copper-based metallurgy. The mesh-like interconnection structure comprises conductive pads interconnected by conductive lines at each wiring level with each pad conductively connected to its adjacent pad at the next wiring level by a plurality of conductive vias. The conductive pads, lines and vias are fabricated during the normal BEOL wiring level integration process. The reinforcing structure provides both vertical and horizontal reinforcement and may be fabricated on the periphery of the active device region or within open regions of the device that are susceptible to delamination and cracking.

Abstract: A mesh-like reinforcing structure to inhibit delamination and cracking is fabricated in a multilayer semiconductor device using low-k dielectric materials and copper-based metallurgy. The mesh-like interconnection structure comprises conductive pads interconnected by conductive lines at each wiring level with each pad conductively connected to its adjacent pad at the next wiring level by a plurality of conductive vias. The conductive pads, lines and vias are fabricated during the normal BEOL wiring level integration process. The reinforcing structure provides both vertical and horizontal reinforcement and may be fabricated on the periphery of the active device region or within open regions of the device that are susceptible to delamination and cracking.

Abstract: A mesh-like reinforcing structure to inhibit delamination and cracking is fabricated in a multilayer semiconductor device using low-k dielectric materials and copper-based metallurgy. The mesh-like interconnection structure comprises conductive pads interconnected by conductive lines at each wiring level with each pad conductively connected to its adjacent pad at the next wiring level by a plurality of conductive vias. The conductive pads, lines and vias are fabricated during the normal BEOL wiring level integration process. The reinforcing structure provides both vertical and horizontal reinforcement and may be fabricated on the periphery of the active device region or within open regions of the device that are susceptible to delamination and cracking.

Abstract: A metal alloy solder ball comprising a first metal and a second metal, the first metal having a sputtering yield greater than the second metal. The solder ball comprises a bulk portion having a bulk ratio of the first metal to the second metal, an outer surface, and a surface gradient having a depth and a gradient ratio of the first metal to the second metal that is less than the bulk ratio. The gradient ratio increases along the surface gradient depth from a minimum at the outer surface. The solder ball may be formed by the process of exposing the ball to energized ions of a sputtering gas for an effective amount of time to form the surface gradient.

Abstract: A method for forming a flip-chip-on-board assembly. An integrated circuit (IC) chip having a polyimide passivation layer is joined to a chip carrier via a plurality of solder bumps which electrically connect a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between a surface of the passivation layer and a surface of the chip carrier. A plasma is applied, to chemically modify the surface of the chip carrier and the passivation layer of the IC chip substantially without roughening the surface of the passivation layer. The plasma is either an O2 plasma or a microwave-generated Ar and N2O plasma. An underfill encapsulant material is applied to fill the space. The plasma treatment may be performed after the step of joining. Then, the chip and chip carrier are treated with the plasma simultaneously. Alternatively, the IC chip and chip carrier may be treated with the plasma before they are joined to one another.

Abstract: A method for forming a flip-chip-on-board assembly. An integrated circuit (IC) chip having a polyimide passivation layer is joined to a chip carrier via a plurality of solder bumps which electrically connect a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between a surface of the passivation layer and a surface of the chip carrier. A plasma is applied, to chemically modify the surface of the chip carrier and the passivation layer of the IC chip substantially without roughening the surface of the passivation layer. The plasma is either an O2 plasma or a microwave-generated Ar and N2O plasma. An underfill encapsulant material is applied to fill the space. The plasma treatment may be performed after the step of joining. Then, the chip and chip carrier are treated with the plasma simultaneously. Alternatively, the IC chip and chip carrier may be treat with the plasma before they are joined to one another.

Abstract: A metal alloy solder ball comprising a first metal and a second metal, the first metal having a sputtering yield greater than the second metal. The solder ball comprises a bulk portion having a bulk ratio of the first metal to the second metal, an outer surface, and a surface gradient having a depth and a gradient ratio of the first metal to the second metal that is less than the bulk ratio. The gradient ratio increases along the surface gradient depth from a minimum at the outer surface. The solder ball may be formed by the process of exposing the ball to energized ions of a sputtering gas for an effective amount of time to form the surface gradient.