Abstract: A method includes embedding clothing with at least one sensor and at least one control unit; a power unit powering on the at least one sensor and the at least one control unit; the at least one sensor monitoring a sensed condition; the at least one control unit conducting a heat prediction based on the sensed condition; and the at least one control unit controlling threads within the clothing based on the heat prediction to actively adjust properties of the clothing.

Abstract: An SSD has a plurality of dies, with each die having a storage capacity. The storage capacity of each die is divided into a primary capacity and a spare capacity. A primary die has a maximum primary capacity, and a sum of the spare capacities of the remaining dies is greater than the maximum primary capacity. Data stored on the SSD is distributed among the primary capacities of the dies. When a failure of a first die is detected, data stored on the failed first die is migrated to the spare capacity of at least one of the remaining dies.

Abstract: A method for detecting a software-race condition in a program includes copying a state of a transaction of the program from a first core of a multi-core processor to at least one additional core of the multi-core processor, running the transaction, redundantly, on the first core and the at least one additional core given the state, outputting a result of the first core and the at least one additional core, and detecting a difference in the results between the first core and the at least one additional core, wherein the difference indicates the software-race condition.

Abstract: A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory access resulting in a cache miss in a given processor, the processor determines whether a memory region being accessed is marked as directory-based. Responsive to the given processor determining the memory region is marked as directory-based, the given processor accesses a directory entry corresponding to the memory region to identify a home chip for the page using a directory-based protocol. The given processor forwards the memory access request to the home chip to perform the memory access.

Abstract: A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory access resulting in a cache miss in a given processor, the processor determines whether a memory region being accessed is marked as directory-based. Responsive to the given processor determining the memory region is marked as directory-based, the given processor accesses a directory entry corresponding to the memory region to identify a home chip for the page using a directory-based protocol. The given processor forwards the memory access request to the home chip to perform the memory access.

Abstract: Apparatus and methods are disclosed that enable the allocation of a cache portion of a memory buffer to be utilized by an on-cache function controller (OFC) to execute processing functions on “main line” data. A particular method may include receiving, at a memory buffer, a request from a memory controller for allocation of a cache portion of the memory buffer. The method may also include acquiring, by an on-cache function controller (OFC) of the memory buffer, the requested cache portion of the memory buffer. The method may further include executing, by the OFC, a processing function on data stored at the cache portion of the memory buffer.

Abstract: Embodiments relate to thread-based cache content savings for task switching in a computer processor. An aspect includes determining a cache entry in a cache of the computer processor that is owned by the first thread, wherein the determination is made based on a hardware thread identifier (ID) of the first thread matching a hardware thread ID in the cache entry. Another aspect includes determining whether the determined cache entry is eligible for prefetching. Yet another aspect includes, based on determining that the determined cache entry is eligible for prefetching, setting a marker in the cache entry to active.

Abstract: A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.

Abstract: A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.

Abstract: There is provided an apparatus, a method and computer program product for managing one or more components of an electronic machine. A user connects one or more components to an electronic machine in parallel. The electronic machine determines whether the components are failed. A latch device, attached to each component, automatically locks one or more of the components to the electronic machine if the one or more of the components are not failed. The electromechanical latch automatically releases the one or more of the components from the electronic machine if the one or more of the components are failed.

Abstract: Apparatus and methods are disclosed that enable the allocation of a cache portion of a memory buffer to be utilized by an on-cache function controller (OFC) to execute processing functions on “main line” data. A particular method may include receiving, at a memory buffer, a request from a memory controller for allocation of a cache portion of the memory buffer. The method may also include acquiring, by an on-cache function controller (OFC) of the memory buffer, the requested cache portion of the memory buffer. The method may further include executing, by the OFC, a processing function on data stored at the cache portion of the memory buffer.

Abstract: Embodiments relate to a prefetch threshold for cache restoration. An aspect includes determining, based on a task switch from an outgoing task to a current task in a processor, a prefetch threshold for a next task, the prefetch threshold corresponding to an expected runtime of the current task and an amount of time required to prefetch data for the next task. Another aspect includes starting prefetching for the next task while the current task is executing based on the prefetch threshold.

Abstract: A method includes embedding clothing with at least one sensor and at least one control unit; a power unit powering on the at least one sensor and the at least one control unit; the at least one sensor monitoring a sensed condition; the at least one control unit conducting a heat prediction based on the sensed condition; and the at least one control unit controlling threads within the clothing based on the heat prediction to actively adjust properties of the clothing.

Abstract: A method for detecting errors in hardware including running a transaction on a plurality of cores, wherein each of the cores runs a respective copy of the transaction, periodically synchronizing the transaction on the cores throughout execution of the transaction, comparing results of the transaction on the cores, and determining an error in one or more of the cores.

Abstract: Embodiments relate to thread-based cache content savings for task switching in a computer processor. An aspect includes determining a cache entry in a cache of the computer processor that is owned by the first thread, wherein the determination is made based on a hardware thread identifier (ID) of the first thread matching a hardware thread ID in the cache entry. Another aspect includes determining whether the determined cache entry is eligible for prefetching. Yet another aspect includes, based on determining that the determined cache entry is eligible for prefetching, setting a marker in the cache entry to active.

Abstract: Embodiments relate to a prefetch threshold for cache restoration. An aspect includes determining, based on a task switch from an outgoing task to a current task in a processor, a prefetch threshold for a next task, the prefetch threshold corresponding to an expected runtime of the current task and an amount of time required to prefetch data for the next task. Another aspect includes starting prefetching for the next task while the current task is executing based on the prefetch threshold.

Abstract: An SSD has a plurality of dies, with each die having a storage capacity. The storage capacity of each die is divided into a primary capacity and a spare capacity. A primary die has a maximum primary capacity, and a sum of the spare capacities of the remaining dies is greater than the maximum primary capacity. Data stored on the SSD is distributed among the primary capacities of the dies. When a failure of a first die is detected, data stored on the failed first die is migrated to the spare capacity of at least one of the remaining dies.

Abstract: A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.

Abstract: A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.

Abstract: An SSD has a plurality of dies, with each die having a storage capacity. The storage capacity of each die is divided into a primary capacity and a spare capacity. A primary die has a maximum primary capacity, and a sum of the spare capacities of the remaining dies is greater than the maximum primary capacity. Data stored on the SSD is distributed among the primary capacities of the dies. When a failure of a first die is detected, data stored on the failed first die is migrated to the spare capacity of at least one of the remaining dies.