Patents by Inventor David M. Daly

David M. Daly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8448178
    Abstract: Systems and methods are provided that schedule task requests within a computing system based upon the history of task requests. The history of task requests can be represented by a historical log that monitors the receipt of high priority task request submissions over time. This historical log in combination with other user defined scheduling rules is used to schedule the task requests. Task requests in the computer system are maintained in a list that can be divided into a hierarchy of queues differentiated by the level of priority associated with the task requests contained within that queue. The user-defined scheduling rules give scheduling priority to the higher priority task requests, and the historical log is used to predict subsequent submissions of high priority task requests so that lower priority task requests that would interfere with the higher priority task requests will be delayed or will not be scheduled for processing.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: David M Daly, Peter A Franaszek, Luis A Lastras-Montano
  • Publication number: 20130019085
    Abstract: A mechanism is provided for reducing a penalty for executing a correct branch of a branch instruction. An execution unit in a processor of a data processing system executes a first branch of the branch instruction from a main thread of a processor and executes a second branch of the branch instruction from an assist thread of the processor. The execution unit determines whether the main thread is a correct branch of the branch instruction or the assist thread is the correct branch of the branch instruction. Responsive to the assist thread being the correct branch of the branch instruction, the execution unit pauses execution of the branch instruction on both the main thread and the assist thread. The execution unit then properly inherits a context of the main thread in order that execution of the second branch may continue.
    Type: Application
    Filed: July 12, 2011
    Publication date: January 17, 2013
    Applicant: International Business Machines Corporation
    Inventors: Harold W. Cain, III, David M. Daly, Michael C. Huang, Jose E. Moreira, IL Park
  • Publication number: 20130019083
    Abstract: A mechanism is provided for redundant execution of a set of instructions. A redundant execution begin (rbegin) instruction to be executed by a first hardware thread on the first processor is identified in the set of instructions. The set of instructions immediately after the rbegin instruction are executed on the first hardware thread and on a second hardware thread. Responsive to both the first processor and the second processor ending execution of the set of instructions, responsive to a first set of cache lines in a first speculative store matching a second set of cache lines in a second speculative store, and responsive to a first set of register states in a first status register matching a second set of register states in a second status register, dirty lines in the first speculative store are committed thereby committing a redundant transaction state to an architectural state.
    Type: Application
    Filed: July 11, 2011
    Publication date: January 17, 2013
    Applicant: International Business Machines Corporation
    Inventors: Harold W. Cain, III, David M. Daly, Kattamuri Ekanadham, Michael C. Huang, Jose E. Moreira, Mauricio J. Serrano
  • Publication number: 20120203968
    Abstract: A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a system memory and includes a physical write queue from which the memory controller writes data to the system memory. The memory controller initiates accesses to the lowest level cache to place into the physical write queue selected cachelines having spatial locality with data present in the physical write queue.
    Type: Application
    Filed: April 16, 2012
    Publication date: August 9, 2012
    Applicant: International Business Machines Corporation
    Inventors: David M. DALY, Benjiman L. GOODMAN, Hillery C. HUNTER, William J. STARKE, Jeffrey A. STUECHELI
  • Publication number: 20120203969
    Abstract: A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory controller includes a physical read queue that buffers data read from the system memory via the memory bus and a physical write queue that buffers data to be written to the system memory via the memory bus. The memory controller grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory.
    Type: Application
    Filed: April 16, 2012
    Publication date: August 9, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: DAVID M. DALY, BENJIMAN L. GOODMAN, HILLERY C. HUNTER, WILLIAM J. STARKE, JEFFREY A. STUECHELI
  • Publication number: 20120180060
    Abstract: Systems and methods are provided that schedule task requests within a computing system based upon the history of task requests. The history of task requests can be represented by a historical log that monitors the receipt of high priority task request submissions over time. This historical log in combination with other user defined scheduling rules is used to schedule the task requests. Task requests in the computer system are maintained in a list that can be divided into a hierarchy of queues differentiated by the level of priority associated with the task requests contained within that queue. The user-defined scheduling rules give scheduling priority to the higher priority task requests, and the historical log is used to predict subsequent submissions of high priority task requests so that lower priority task requests that would interfere with the higher priority task requests will be delayed or will not be scheduled for processing.
    Type: Application
    Filed: March 20, 2012
    Publication date: July 12, 2012
    Applicant: International Business Machines Corporation
    Inventors: David M. DALY, Peter A. FRANASZEK, Luis A. LASTRAS-MONTANO
  • Patent number: 8185899
    Abstract: Systems and methods are provided that schedule task requests within a computing system based upon the history of task requests. The history of task requests can be represented by a historical log that monitors the receipt of high priority task request submissions over time. This historical log in combination with other user defined scheduling rules is used to schedule the task requests. Task requests in the computer system are maintained in a list that can be divided into a hierarchy of queues differentiated by the level of priority associated with the task requests contained within that queue. The user-defined scheduling rules give scheduling priority to the higher priority task requests, and the historical log is used to predict subsequent submissions of high priority task requests so that lower priority task requests that would interfere with the higher priority task requests will be delayed or will not be scheduled for processing.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: May 22, 2012
    Assignee: International Business Machines Corporation
    Inventors: David M. Daly, Peter A. Franaszek, Luis A. Lastras-Montano
  • Publication number: 20110276762
    Abstract: A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a system memory and includes a physical write queue from which the memory controller writes data to the system memory. The memory controller initiates accesses to the lowest level cache to place into the physical write queue selected cachelines having spatial locality with data present in the physical write queue.
    Type: Application
    Filed: May 7, 2010
    Publication date: November 10, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: DAVID M. DALY, BENJIMAN L. GOODMAN, HILLERY C. HUNTER, WILLIAM J. STARKE, JEFFREY A. STUECHELI
  • Publication number: 20110276763
    Abstract: A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory controller includes a physical read queue that buffers data read from the system memory via the memory bus and a physical write queue that buffers data to be written to the system memory via the memory bus. The memory controller grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory.
    Type: Application
    Filed: May 7, 2010
    Publication date: November 10, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: DAVID M. DALY, BENJIMAN L. GOODMAN, HILLERY C. HUNTER, WILLIAM J. STARKE, JEFFREY A. STUECHELI
  • Publication number: 20080222640
    Abstract: Systems and methods are provided that schedule task requests within a computing system based upon the history of task requests. The history of task requests can be represented by a historical log that monitors the receipt of high priority task request submissions over time. This historical log in combination with other user defined scheduling rules is used to schedule the task requests. Task requests in the computer system are maintained in a list that can be divided into a hierarchy of queues differentiated by the level of priority associated with the task requests contained within that queue. The user-defined scheduling rules give scheduling priority to the higher priority task requests, and the historical log is used to predict subsequent submissions of high priority task requests so that lower priority task requests that would interfere with the higher priority task requests will be delayed or will not be scheduled for processing.
    Type: Application
    Filed: March 7, 2007
    Publication date: September 11, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David M. Daly, Peter A. Franaszek, Luis A. Lastras-Montano
  • Patent number: 4145082
    Abstract: A support cradle for supporting a person seated in a chair by cradling the upper legs of the person, and maintaining the legs in a desired passive restraint arranged so that if the person moves the hips or legs in an abnormal degree such as excessive hip flexion, hip adduction, hip internal rotation, hip extension, scissoring or the like, the cradle will restrain such movement. The cradle provides no restraint so long as normal sitting posture is maintained. The cradle is especially useful in treatment and management of patients with neurogenic movement disorders which manifest with spasticity and abnormal movement patterns such as with spinal cord injury or in cerebral palsy.
    Type: Grant
    Filed: April 11, 1977
    Date of Patent: March 20, 1979
    Assignee: David M. Daly
    Inventors: David M. Daly, Cynthia L. Stone