Patents by Inventor David M. Daly
David M. Daly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160321180Abstract: A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory access resulting in a cache miss in a given processor, the processor determines whether a memory region being accessed is marked as directory-based. Responsive to the given processor determining the memory region is marked as directory-based, the given processor accesses a directory entry corresponding to the memory region to identify a home chip for the page using a directory-based protocol. The given processor forwards the memory access request to the home chip to perform the memory access.Type: ApplicationFiled: June 19, 2015Publication date: November 3, 2016Inventor: David M. Daly
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Publication number: 20160321191Abstract: A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory access resulting in a cache miss in a given processor, the processor determines whether a memory region being accessed is marked as directory-based. Responsive to the given processor determining the memory region is marked as directory-based, the given processor accesses a directory entry corresponding to the memory region to identify a home chip for the page using a directory-based protocol. The given processor forwards the memory access request to the home chip to perform the memory access.Type: ApplicationFiled: April 30, 2015Publication date: November 3, 2016Inventor: David M. Daly
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Patent number: 9471428Abstract: An SSD has a plurality of dies, with each die having a storage capacity. The storage capacity of each die is divided into a primary capacity and a spare capacity. A primary die has a maximum primary capacity, and a sum of the spare capacities of the remaining dies is greater than the maximum primary capacity. Data stored on the SSD is distributed among the primary capacities of the dies. When a failure of a first die is detected, data stored on the failed first die is migrated to the spare capacity of at least one of the remaining dies.Type: GrantFiled: May 6, 2014Date of Patent: October 18, 2016Assignee: International Business Machines CorporationInventors: Diyanesh B. Chinnakkonda Vidyapoornachary, David M. Daly, Gary A. Tressler
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Patent number: 9459979Abstract: A method for detecting errors in hardware including running a transaction on a plurality of cores, wherein each of the cores runs a respective copy of the transaction, synchronizing the transaction on the cores, comparing results of the transaction on the cores, and determining an error in one or more of the cores.Type: GrantFiled: August 8, 2013Date of Patent: October 4, 2016Assignee: International Business Machines CorporationInventors: Harold W. Cain, III, David M. Daly, Kattamuri Ekanadham, Michael C. Huang, Jose E. Moreira, Mauricio J. Serrano
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Patent number: 9448835Abstract: Embodiments relate to thread-based cache content savings for task switching in a computer processor. An aspect includes determining a cache entry in a cache of the computer processor that is owned by the first thread, wherein the determination is made based on a hardware thread identifier (ID) of the first thread matching a hardware thread ID in the cache entry. Another aspect includes determining whether the determined cache entry is eligible for prefetching. Yet another aspect includes, based on determining that the determined cache entry is eligible for prefetching, setting a marker in the cache entry to active.Type: GrantFiled: October 30, 2014Date of Patent: September 20, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harold W. Cain, III, David M. Daly, Brian R. Prasky, Vijayalakshmi Srinivasan
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Patent number: 9436501Abstract: Embodiments relate to thread-based cache content savings for task switching in a computer processor. An aspect includes determining a cache entry in a cache of the computer processor that is owned by the first thread, wherein the determination is made based on a hardware thread identifier (ID) of the first thread matching a hardware thread ID in the cache entry. Another aspect includes determining whether the determined cache entry is eligible for prefetching. Yet another aspect includes, based on determining that the determined cache entry is eligible for prefetching, setting a marker in the cache entry to active.Type: GrantFiled: August 26, 2014Date of Patent: September 6, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harold W. Cain, III, David M. Daly, Brian R. Prasky, Vijayalakshmi Srinivasan
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Patent number: 9424192Abstract: A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.Type: GrantFiled: April 2, 2015Date of Patent: August 23, 2016Assignee: International Business Machines CorporationInventors: David M. Daly, Vijayalakshmi Srinivasan
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Patent number: 9411730Abstract: A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.Type: GrantFiled: June 22, 2015Date of Patent: August 9, 2016Assignee: International Business Machines CorporationInventors: David M. Daly, Vijayalakshmi Srinivasan
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Publication number: 20160147639Abstract: A method for detecting a software-race condition in a program includes copying a state of a transaction of the program from a first core of a multi-core processor to at least one additional core of the multi-core processor, running the transaction, redundantly, on the first core and the at least one additional core given the state, outputting a result of the first core and the at least one additional core, and detecting a difference in the results between the first core and the at least one additional core, wherein the difference indicates the software-race condition.Type: ApplicationFiled: January 30, 2016Publication date: May 26, 2016Inventors: Harold W. Cain, III, David M. Daly, Michael C. Huang, Kattamuri Ekanadham, Jose E. Moreira, Mauricio J. Serrano
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Patent number: 9311228Abstract: A system and method for reducing power consumption of memory chips outside of a host processor device inoperative communication with the memory chips via a memory controller. The memory can operate in modes, such that via the memory controller, the stored data can be localized and moved at various granularities, among ranks established in the chips, to result in fewer operating ranks. Memory chips may then be turned on and off based on host memory access usage levels at each rank in the chip. Host memory access usage levels at each rank in the chip is tracked by performance counters established for association with each rank of a memory chip. Turning on and off of the memory chips is based on a mapping maintained between ranks and address locations corresponding to sub-sections within each rank receiving the host processor access requests.Type: GrantFiled: April 4, 2012Date of Patent: April 12, 2016Assignee: International Business Machines CorporationInventors: David M. Daly, Tejas Karkhanis, Valentina Salapura
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Patent number: 9304863Abstract: A method of backstepping through a program execution includes dividing the program execution into a plurality of epochs, wherein the program execution is performed by an active core, determining, during a subsequent epoch of the plurality of epochs, that a rollback is to be performed, performing the rollback including re-executing a previous epoch of the plurality of epochs, wherein the previous epoch includes one or more instructions of the program execution stored by a checkpointing core, and adjusting a granularity of the plurality of epochs according to a frequency of the rollback.Type: GrantFiled: June 27, 2013Date of Patent: April 5, 2016Assignee: International Business Machines CorporationInventors: Harold W. Cain, III, David M. Daly, Kattamuri Ekanadham, Jose E. Moreira, Mauricio J. Serrano
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Publication number: 20160092331Abstract: A method for detecting errors in hardware including running a transaction on a plurality of cores, wherein each of the cores runs a respective copy of the transaction, periodically synchronizing the transaction on the cores throughout execution of the transaction, comparing results of the transaction on the cores, and determining an error in one or more of the cores.Type: ApplicationFiled: December 9, 2015Publication date: March 31, 2016Inventors: Harold W. Cain, III, David M. Daly, Michael C. Huang, Kattamuri Ekanadham, Jose E. Moreira, Mauricio J. Serrano
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Publication number: 20160062899Abstract: Embodiments relate to thread-based cache content savings for task switching in a computer processor. An aspect includes determining a cache entry in a cache of the computer processor that is owned by the first thread, wherein the determination is made based on a hardware thread identifier (ID) of the first thread matching a hardware thread ID in the cache entry. Another aspect includes determining whether the determined cache entry is eligible for prefetching. Yet another aspect includes, based on determining that the determined cache entry is eligible for prefetching, setting a marker in the cache entry to active.Type: ApplicationFiled: August 26, 2014Publication date: March 3, 2016Inventors: Harold W. Cain, III, David M. Daly, Brian R. Prasky, Vijayalakshmi Srinivasan
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Publication number: 20160062791Abstract: Embodiments relate to thread-based cache content savings for task switching in a computer processor. An aspect includes determining a cache entry in a cache of the computer processor that is owned by the first thread, wherein the determination is made based on a hardware thread identifier (ID) of the first thread matching a hardware thread ID in the cache entry. Another aspect includes determining whether the determined cache entry is eligible for prefetching. Yet another aspect includes, based on determining that the determined cache entry is eligible for prefetching, setting a marker in the cache entry to active.Type: ApplicationFiled: October 30, 2014Publication date: March 3, 2016Inventors: Harold W. Cain, III, David M. Daly, Brian R. Prasky, Vijayalakshmi Srinivasan
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Patent number: 9251014Abstract: A method for detecting a software-race condition in a program includes copying a state of a transaction of the program from a first core of a multi-core processor to at least one additional core of the multi-core processor, running the transaction, redundantly, on the first core and the at least one additional core given the state, outputting a result of the first core and the at least one additional core, and detecting a difference in the results between the first core and the at least one additional core, wherein the difference indicates the software-race condition.Type: GrantFiled: August 8, 2013Date of Patent: February 2, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harold W. Cain, III, David M. Daly, Michael C. Huang, Kattamuri Ekanadham, Jose E. Moreira, Mauricio J. Serrano
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Publication number: 20150370706Abstract: Apparatus and methods are disclosed that enable the allocation of a cache portion of a memory buffer to be utilized by an on-cache function controller (OFC) to execute processing functions on “main line” data. A particular method may include receiving, at a memory buffer, a request from a memory controller for allocation of a cache portion of the memory buffer. The method may also include acquiring, by an on-cache function controller (OFC) of the memory buffer, the requested cache portion of the memory buffer. The method may further include executing, by the OFC, a processing function on data stored at the cache portion of the memory buffer.Type: ApplicationFiled: June 18, 2014Publication date: December 24, 2015Inventors: Edgar R. Cordero, David M. Daly, Robert K. Montoye, Saravanan Sethuraman, Diyanesh B. Chinnakkonda Vidyapoornachary
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Publication number: 20150370711Abstract: Apparatus and methods are disclosed that enable the allocation of a cache portion of a memory buffer to be utilized by an on-cache function controller (OFC) to execute processing functions on “main line” data. A particular method may include receiving, at a memory buffer, a request from a memory controller for allocation of a cache portion of the memory buffer. The method may also include acquiring, by an on-cache function controller (OFC) of the memory buffer, the requested cache portion of the memory buffer. The method may further include executing, by the OFC, a processing function on data stored at the cache portion of the memory buffer.Type: ApplicationFiled: December 17, 2014Publication date: December 24, 2015Inventors: Edgar R. Cordero, David M. Daly, Robert K. Montoye, Saravanan Sethuraman, Diyanesh B. Chinnakkonda Vidyapoornachary
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Publication number: 20150338891Abstract: There is provided an apparatus, a method and computer program product for managing one or more components of an electronic machine. A user connects one or more components to an electronic machine in parallel. The electronic machine determines whether the components are failed. A latch device, attached to each component, automatically locks one or more of the components to the electronic machine if the one or more of the components are not failed. The electromechanical latch automatically releases the one or more of the components from the electronic machine if the one or more of the components are failed.Type: ApplicationFiled: May 23, 2014Publication date: November 26, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harold W. Cain, III, David M. Daly, Jose E. Moreira
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Publication number: 20150324262Abstract: An SSD has a plurality of dies, with each die having a storage capacity. The storage capacity of each die is divided into a primary capacity and a spare capacity. A primary die has a maximum primary capacity, and a sum of the spare capacities of the remaining dies is greater than the maximum primary capacity. Data stored on the SSD is distributed among the primary capacities of the dies. When a failure of a first die is detected, data stored on the failed first die is migrated to the spare capacity of at least one of the remaining dies.Type: ApplicationFiled: August 20, 2014Publication date: November 12, 2015Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, David M. Daly, Gary A. Tressler
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Publication number: 20150324264Abstract: An SSD has a plurality of dies, with each die having a storage capacity. The storage capacity of each die is divided into a primary capacity and a spare capacity. A primary die has a maximum primary capacity, and a sum of the spare capacities of the remaining dies is greater than the maximum primary capacity. Data stored on the SSD is distributed among the primary capacities of the dies. When a failure of a first die is detected, data stored on the failed first die is migrated to the spare capacity of at least one of the remaining dies.Type: ApplicationFiled: May 6, 2014Publication date: November 12, 2015Applicant: International Business Machines CorporationInventors: Diyanesh B. Chinnakkonda Vidyapoornachary, David M. Daly, Gary A. Tressler