Abstract: Described embodiments provide a system having a plurality of processor cores and common memory in direct communication with the cores. A source processing core communicates with a task destination core by generating a task message for the task destination core. The task source core transmits the task message directly to a receiving processing core adjacent to the task source core. If the receiving processing core is not the task destination core, the receiving processing core passes the task message unchanged to a processing core adjacent the receiving processing core. If the receiving processing core is the task destination core, the task destination core processes the message.

Abstract: Described embodiments provide a method of assigning tasks to queues of a processing core. Tasks are assigned to a queue by sending, by a source processing core, a new task having a task identifier. A destination processing core receives the new task and determines whether another task having the same identifier exists in any of the queues corresponding to the destination processing core. If another task with the same identifier as the new task exists, the destination processing core assigns the new task to the queue containing a task with the same identifier as the new task. If no task with the same identifier as the new task exists in the queues, the destination processing core assigns the new task to the queue having the fewest tasks. The source processing core writes the new task to the assigned queue. The destination processing core executes the tasks in its queues.

Abstract: Improved timeout table mechanism are disclosed. By way of example, a method for providing timeout delays for data queues in a processing system includes the following steps. A timeout structure is maintained. The timeout structure includes two or more groups, each group including two or more bins, each bin having a range of timeout delay values associated therewith, each group having a weight associated therewith, the weight of each group being based on a rate and a quantity of queues assignable to each group. A timeout delay value to be assigned to a data queue in the processing system is selected.

Abstract: Improved techniques are disclosed for performing an in-service upgrade of software associated with a network or packet processor. By way of example, a method of performing an in-service upgrade of code, storable in a memory associated with a packet processor and executable on the packet processor, from a first code version to a second code version, includes the following steps. A first step includes preparing for the upgrade by generating one or more write operations to effectuate the code upgrade from the first code version to the second code version. A second step includes updating the code from the first code version to the second code version by propagating the one or more write operations to the packet processor. A third step includes cleaning up after the updating step by reclaiming one or more memory locations available after the update step. As such, the storage of only a single version of the code in the memory associated with the packet processor is required.

Abstract: Methods and apparatus for controlling latency variation of packets received in a packet transfer network are provided. A plurality of packets is received at a network element of a receive node of the packet transfer network. A time-stamp is provided for each of the plurality of packets. An egress delay time is computed at a scheduler of the network element for each of the plurality of packets in accordance with each corresponding time-stamp to provide a substantially constant latency for the plurality of packets upon egression from the network element.

Abstract: A peripheral connectable to a processing device includes a housing and network interface circuitry at least partially enclosed within the housing, the network interface circuitry being utilizable by the processing device to establish a connection between the processing device and a network. The peripheral further includes peripheral circuitry disposed within the housing and adapted to perform at least a portion of at least one of an input function and an output function for the processing device in a manner unrelated to utilization of the network interface circuitry by the processing device. In an illustrative embodiment, the network interface circuitry comprises a wireless local area network (LAN) interface card, module or access point, the processing device comprises a computer, and the peripheral comprises a keyboard, monitor, speaker, docking station or other peripheral connectable to the computer.

Abstract: Backpressure information is communicated from a physical layer device to a link layer device in a communication system by generating a flow control message in the physical layer device responsive to a detected condition relating to at least a given one of a plurality of queues of the physical layer device, and transmitting the flow control message from the physical layer device to the link layer device. The flow control message may comprises backpressure information associated with a given egress queue of the physical layer device and is transmitted from the physical layer device to the link layer device as an in-band message over an interface between the physical layer device and the link layer device. Multiple-rate traffic shaping or other types of traffic shaping may be provided responsive to the flow control message.

Abstract: A method for use in a fault tolerant environment for assuring that devices within the environment switch between primary and back-up systems in response to remotely generated control signals. In one embodiment, the inventive system uses a binary code in the form of a pair of different frequency signals, i.e., a binary zero is represented by one frequency and a binary one is represented by another frequency. The signals may be continuous or may be sent in timed bursts. At the individual devices, which may comprise line cards, a receiver is provided to detect the presence of the signals.

Abstract: A processor includes a scheduler operative to schedule data blocks for transmission from a plurality of queues or other transmission elements, utilizing at least a first table and a second table. The first table may comprise at least first and second first-in first-out (FIFO) lists of entries corresponding to transmission elements for which data blocks are to be scheduled in accordance with a first scheduling algorithm, such as a weighted fair queuing scheduling algorithm. The scheduler maintains a first table pointer identifying at least one of the first and second lists of the first table as having priority over the other of the first and second lists of the first table. The second table includes a plurality of entries corresponding to transmission elements for which data blocks are to be scheduled in accordance with a second scheduling algorithm, such as a constant bit rate or variable bit rate scheduling algorithm.

Abstract: A processor includes scheduling circuitry for scheduling data blocks for transmission from multiple transmission elements, and traffic shaping circuitry coupled to the scheduling circuitry and operative to establish a traffic shaping requirement for the transmission of the data blocks from the transmission elements. The scheduling circuitry is configured for utilization of at least one time slot table which includes multiple locations, each corresponding to a transmission time slot. The scheduling circuitry is operative in conjunction with the time slot table to schedule the data blocks for transmission in a manner that substantially maintains the traffic shaping requirement established by the traffic shaping circuitry even in the presence of collisions between requests from the transmission elements for each of one or more of the time slots.

Abstract: A head of line blockage avoidance system for use with network systems that employ packets having an associated priority and a method of operation thereof. In one embodiment, the head of line blockage avoidance system includes: (1) m inputs, m numbering at least two, configured to receive the packets, (2) n packet first-in-first-out buffers (FIFOs), n numbering at least three, each of the packet FIFOs configured to receive at least one of the packets from the m inputs, (3) a priority summarizer configured to generate a priority summary of the packets within the m inputs and the n packet FIFOs, and (4) a scheduler configured to cause one of the n packet FIFOs to be queued for processing based on the priority summary.

Abstract: Methods and apparatus for controlling latency variation of packets received in a packet transfer network are provided. A plurality of packets is received at a network element of a receive node of the packet transfer network. A time-stamp is provided for each of the plurality of packets. An egress delay time is computed at a scheduler of the network element for each of the plurality of packets in accordance with each corresponding time-stamp to provide a substantially constant latency for the plurality of packets upon egression from the network element.

Abstract: In a system including a processor and memory coupled to the processor, a method of device failure analysis includes the steps of: upon each error detected within a test series performed on a device, the processor storing within a table in the memory an address at which the error occurred in the device and storing a bit position of each failed bit corresponding to that address; for each unique address at which at least one error occurred, determining how many different bit positions corresponding to the address failed during the test series; and based on results of the test series, determining whether the device failed the test series.

Abstract: A switching system for a data traffic network. A plurality of line cards provide input and output connections to a plurality of data lines and further are connected to at least two switch fabrics, one of which is designated the active switch fabric and the other designated the standby switch fabric. Data traffic is switched between the plurality of input and output line cards by the active switch fabric. When it is desired to change the active switch fabric assignment, for example due to a fault in the switch fabric, data transmissions into the active switch fabric are terminated and a drain timer is started. When the drain timer times out or the active switch provides an indication that it is empty, the active switch fabric assignment is swapped to the standby switch fabric and data is then switched through the newly assigned active switch fabric.

Abstract: A network-based apparatus for imposing a minimum transmit latency on data packets of a prescribed data type on a network includes at least one processor. The processor is operative: (i) to receive a data packet of the prescribed data type; (ii) to determine an elapsed time since an arrival of the received data packet at the apparatus; (iii) when the elapsed time is equal to or greater than the minimum transmit latency, to transmit the data packet; and (iv) when the elapsed time is less than the minimum transmit latency, to wait an amount of time at least equal to a difference between the elapsed time and the minimum transmit latency and then to transmit the data packet. The apparatus further includes memory coupled to the processor, the memory being configurable for storing data utilized by the processor.

Abstract: A fast pattern processor having an internal function bus and an external function bus. In one embodiment, a fast pattern processor includes: (1) an internal function bus, (2) an external function bus, (3) a context memory having a block buffer and a argument signature register wherein the block buffer includes processing blocks associated with a protocol data unit (PDU), (4) a pattern processing engine, associated with the context memory, that performs pattern matching and (5) a function interface system having (5A) a controller arbitration subsystem and (5B) a dispatch subsystem.

Abstract: A processor includes scheduling circuitry and an associated interval computation element. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, and is configured for utilization of at least one time slot table in scheduling the data blocks for transmission. The interval computation element, which may be implemented as a script processor, is operative to determine an interval for transmission of one or more data blocks associated with corresponding locations in the time slot table. The transmission interval is adjustable under control of the interval computation element so as to facilitate the maintenance of a desired service level for one or more of the transmission elements.

Abstract: A processor includes scheduling circuitry for scheduling data blocks for transmission from a plurality of transmission elements. The scheduling circuitry has at least one time slot table accessible thereto, and is configured for utilization of the time slot table in scheduling the data blocks for transmission. The time slot table includes a plurality of locations, with each of the locations corresponding to a transmission time slot and being configurable for storing identifiers of at least two of the transmission elements. In an illustrative embodiment, a given one of the locations in the time slot table stores in a first portion thereof an identifier of a first one of the transmission elements that has requested transmission of a block of data in the corresponding time slot, and stores in a second portion thereof an identifier of a second one of the transmission elements that has requested transmission of a block of data in the corresponding time slot.

Abstract: A processor includes scheduling circuitry and a priority computation element associated with the scheduling circuitry. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, in accordance with a transmission priority established by the priority computation element. The priority computation element, which may be implemented as a script processor, is operative to determine a transmission priority for one or more constituent transmission elements in a specified group of such transmission elements. The group of transmission elements corresponds to a first level of an n-level hierarchy of transmission elements, with the constituent transmission elements corresponding to at least one lower level of the n-level hierarchy of transmission elements. The transmission priority is preferably made adjustable under software control so as to facilitate the maintenance of a desired service level for one or more of the transmission elements.

Abstract: A multi-protocol bus system and a method of operating the same. In one embodiment, the multi-protocol bus system includes a plurality of protocol indicators associated with an address space, each of the plurality of protocol indicators associated with a segment of the address space and configured to indicate a particular bus protocol. The multi-protocol bus system further includes a bus protocol selection subsystem configured to employ control lines to implement one of the particular bus protocols in accordance with a selected one of the protocol indicators based upon an addressed segment of the address space.