Abstract: A method for use in a fault tolerant environment for assuring that devices within the environment switch between primary and back-up systems in response to remotely generated control signals. In one embodiment, the inventive system uses a binary code in the form of a pair of different frequency signals, i.e., a binary zero is represented by one frequency and a binary one is represented by another frequency. The signals may be continuous or may be sent in timed bursts. At the individual devices, such as the aforementioned line cards, a receiver is provided to detect the presence of the signals. Since the line cards already have receivers to detect the binary signal, modification to detect a frequency signal requires the addition of minimal components. The receiver also includes circuitry for reporting the status of the card and such circuitry can be used to report to the remote controller whether the signals are reaching the line card.

Abstract: A system and method for memory management in a high-speed network environment. Multiple packets are interleaved in data streams and sent to a Memory Manager System. Read and write requests are queued in FIFO buffers. Subsets of these requests are grouped and ordered to optimize processing. This method employs a special arbitration scheme between read and write accesses. Read and write requests are treated as atomic. Memory bank selection is optimized for the request being processed. Alternating between memory bank sets is done to minimize bank conflicts. Link list updates are pipelined. Multiple independent link lists may be supported with the inclusion of a link list identifier. Arbitration between read and write requests continues until the group is exhausted. Then, processing is repeated for the next requests in the BRAM (buffer memories).

Abstract: A method is disclosed for free memory allocation in a linked list memory scheme. Free lists are link lists designating available memory for data storage. This method leverages the ability to read memory while concurrently updating a pointer to the next location. Multiple free lists are used to reduce the number of cycles necessary to allocate memory. The number of entries in each free list is tracked. When memory becomes available, it is spliced into the shortest free list to achieve balance between the free lists. The free list structure disclosed consists of head, head +1, and tail pointers where head +1 is the next logical address pointed to from the head pointer location. The free list consists only of the head and tail pointers. Each link list structure of memory to be freed contains the head, head +1, and tail pointers. This allows us to simultaneously allocate and free with only 1 memory cycle.

Abstract: A switching system for a data traffic network. A plurality of line cards provide input and output connections to a plurality of data lines and further are connected to at least two switch fabrics, one of which is designated the active switch fabric and the other designated the standby switch fabric. Data traffic is switched between the plurality of input and output line cards by the active switch fabric. When it is desired to change the active switch fabric assignment, for example due to a fault in the switch fabric, data transmissions into the active switch fabric are terminated and a drain timer is started. When the drain timer times out or the active switch provides an indication that it is empty, the active switch fabric assignment is swapped to the standby switch fabric and data is then switched through the newly assigned active switch fabric.

Abstract: A scheduler for shared network resources implementing a plurality of user selectable data scheduling schemes within a single hardware device. The schemes include strict priority, priority for one class plus smooth deficit weighted round robin for the other classes, bandwidth limited strict priority and smooth deficit weighted round robin for all user classes. The network operator selects one of the four schemes by enabling or disabling certain bits in the hardware device.

Abstract: An apparatus and method for moving and/or resizing logical buffers that comprise a memory space without the loss of data. Each buffer comprises a linear and contiguous set of storage locations, and operates according to a FIFO priority scheme, using a read address pointer to indicate the location from which data is read from the buffer and a write address pointer indicating the address into which data is written. A buffer is relocated or resized within the memory space by changing the base location address (defining the lowest storage location comprising the buffer) and/or the top location address (defining the highest memory location within the buffer) into free storage locations. To accomplish this relocation or resizing without the loss of data, the read address is first checked to determine if it bears an appropriate relationship to the new base and top memory locations.

Abstract: A multicast group list (i.e., destination node address list) for a network device is circularly linked such that the list can be entered at any point and traversed back to the entry point. The list traversal is then terminated as the entire list has been processed. The data packet received at the network device for transmission to the multicast group can indicate the entry point, although there are other techniques for determining the entry point. The destination node address for the entry point is skipped, that is the multicast data packet is not transmitted to the entry point destination address.

Abstract: A method and apparatus for providing paired or shadowed shared memory within UNIX and UNIX-like environments is provided. For the present invention shared memory segments, established using System V-like shared memory commands, are registered or paired. Once paired checkpointing operations may be performed by pushing or pulling data between paired segments. These checkpointing operations may be synchronous or asynchronous. The present invention also allows client processes to determine the status of shared memory segments and the status of checkpointing requests.

Abstract: A non-blocking crossbar for packet based networks and a method of operation thereof. In one embodiment, the non-blocking crossbar includes: (1) n inputs, n numbering at least two, (2) n outputs, each of the outputs having a destination first-in, first-out buffer (FIFO) and n crossbar FIFOs interposing corresponding ones of the n inputs and the destination FIFO, and (3) a scheduler configured to cause a packet to be transmitted from one of the inputs toward one of the outputs only when both the destination FIFO associated therewith and an interposing one of the crossbar FIFOs are available to contain the packet.

Abstract: A voice packet processor for use with voice applications employing a fast pattern processor (FPP) and a routing switch processor (RSP) that receive and transmit protocol data units (PDUs) and a method of operation thereof. In one embodiment, the voice packet processor includes (1) a voice packet controller (VPC) configured to receive the PDUs from the FPP and queue the PDUs for processing, (2) a voice packet parser configured to receive the PDUs that are ATM adaptation layer 2 (AAL2) cells containing voice data from the VPC, parse the AAL2 cells into at least one Common Part Sublayer (CPS) packet and transmit the at least one CPS packet to the RSP, and (3) a voice packet assembler configured to receive the PDUs that are CPS packets from the VPC, assemble the CPS packets into at least one AAL2 Cell and transmit the at least one AAL2 cell to the RSP.

Abstract: A head of line blockage avoidance system for use with network systems that employ packets having an associated priority and a method of operation thereof. In one embodiment, the head of line blockage avoidance system includes: (1) m inputs, m numbering at least two, configured to receive the packets, (2) n packet first-in-first-out buffers (FIFOs), n numbering at least three, each of the packet FIFOs configured to receive at least one of the packets from the m inputs, (3) a priority summarizer configured to generate a priority summary of the packets within the m inputs and the n packet FIFOs, and (4) a scheduler configured to cause one of the n packet FIFOs to be queued for processing based on the priority summary.

Abstract: A function interface system for use with a fast pattern processor having an internal function bus and an external function bus and a method of operating the same. In one embodiment, the function interface system includes a controller arbitration subsystem configured to process an issued function request received from at least one of the internal function bus and the external function bus and a dispatch subsystem configured to retrieve the issued function request and dispatch the issued function request to at least one associated co-processor via the controller arbitration subsystem.

Abstract: A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Abstract: A circular queue is asynchronously accessed and managed by two separate processing elements. Each data element is added to the queue together with a zero data element that both marks the tail of the queue and signifies that the queue is empty. Data elements are removed from the queue in the order in which they were stored (first-in-first-out) and a manner that allows multiple, concurrent access to the queue. When the queue is accessed to remove a data element the element is first tested. If it is non-zero, the removal process continues; if zero, the queue is considered empty. The management of the queue permits dynamic re-sizing (i.e., making the queue larger or smaller) while data elements are being added and/or removed.

Abstract: A multiple processing system, comprises at least a pair of processor units communicatively connected to a number of peripheral devices through a network that includes routing devices interconnected to route information in the form of message packets sent between the processor units and peripheral devices. Data describing the topographical interconnections of the system elements is maintained with the system. A service processor accesses the data, determines therefrom the topographical interconnections forming the network, assigns addresses/identifications to the system elements, and configures the router devices to establish the most direct routes between system elements for message packets sent on the network.

Abstract: A multiprocessor system includes a number of central processing unit (CPUs) and at least one input/output (I/O) device interconnected by routing apparatus for communicating packetized messages therebetween. The messages contain address information identifying the source and destination of the message, and may also contain requests to write to, or read from, storage of a CPU. Protection against errant reads or writes is provided by an access validation method that utilizes access validation information contained in plural entries maintained by each CPU. Each entry provides validation by identifying what elements of the system has read and/or write wccss to the memory of that CPU, without which memory access is denied.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system.

Abstract: A data communicating device, having a number of inputs whereat data is received for communication from one of a number of outputs of the device, includes apparatus for providing two levels of arbitration to select one of the inputs for data communication to an output. The first (lower) level of arbitration bases selection upon a round-robin order; the second (higher) arbitration level selects inputs based upon an indication from an input of an undue wait for access to the output over a period of time. Each input is provided a modulo-N counter, and a digital counter. Each time an input contends for access to an output and loses to selection by the output to another input, the modulo-N counter is incremented by an assigned value for that input. When N is exceed without access, the digital counter is incremented. The content of the counter operates to force the high-level arbitration.

Abstract: A data communicating device, having a number of inputs whereat data is received for communication from one of a number of outputs of the device, includes apparatus for selecting one of the inputs based upon a comparison of accumulated bias values that can change over time when an input is kept waiting. Each input is provided an assigned bias value from which is developed the accumulated bias value that is compared with that of other inputs arbitrating for access to an output. The output selects one of the inputs, based upon the comparison, and the accumulated bias value of the selected input is diminished by the sum of the assigned bias values of the inputs participating in the arbitration, but not selected, while the accumulated bias values of the other participants are each increased by their corresponding assigned bias values.