Abstract: A scheduler for shared network resources implementing a plurality of user selectable data scheduling schemes within a single hardware device. The schemes include strict priority, priority for one class plus smooth deficit weighted round robin for the other classes, bandwidth limited strict priority and smooth deficit weighted round robin for all user classes. The network operator selects one of the four schemes by enabling or disabling certain bits in the hardware device.

Abstract: A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.

Abstract: A process and architecture to simplify the implementation of a high-speed scheduler. A traditional packet based scheduler works the length of the packet. Instead, the present invention uses a transmit queue that determines how many times a portion of a packet needs to be transmitted independent of the process to modify or transform the packet. The packet could be an ATM cell, it could be a fabric cell, or it could be a portion of a frame-based transmission of the packet. As a result, the transmit queue need only determine how many times (times to transmit (TTT)) to schedule transmission of part of the packet. The determined TTT from the transit queue takes into account the packet-based modifications that will be performed on the packet. The TTT is used to determine how many cells the packet needs to be divided into. In another illustrative embodiment, the number of cells or the TTT is determined prior to adding or removing data from the packet.

Abstract: A method is disclosed for free memory allocation in a linked list memory scheme. Free lists are link lists designating available memory for data storage. This method leverages the ability to read memory while concurrently updating a pointer to the next location. Multiple free lists are used to reduce the number of cycles necessary to allocate memory. The number of entries in each free list is tracked. When memory becomes available, it is spliced into the shortest free list to achieve balance between the free lists. The free list structure disclosed consists of head, head +1, and tail pointers where head +1 is the next logical address pointed to from the head pointer location. The free list consists only of the head and tail pointers. Each link list structure of memory to be freed contains the head, head +1, and tail pointers. This allows us to simultaneously allocate and free with only 1 memory cycle.

Abstract: A voice packet processor for use with voice applications employing a fast pattern processor (FPP) and a routing switch processor (RSP) that receive and transmit protocol data units (PDUs) and a method of operation thereof. In one embodiment, the voice packet processor includes (1) a voice packet controller (VPC) configured to receive the PDUs from the FPP and queue the PDUs for processing, (2) a voice packet parser configured to receive the PDUs that are ATM adaptation layer 2 (AAL2) cells containing voice data from the VPC, parse the AAL2 cells into at least one Common Part Sublayer (CPS) packet and transmit the at least one CPS packet to the RSP, and (3) a voice packet assembler configured to receive the PDUs that are CPS packets from the VPC, assemble the CPS packets into at least one AAL2 Cell and transmit the at least one AAL2 cell to the RSP.

Abstract: A virtual segmentation system for use with a routing switch processor and a method of operating the same. In one embodiment, the virtual segmentation system includes a protocol data unit receiver subsystem configured to receive at least a portion of a protocol data unit and assemble the protocol data unit. The virtual segmentation system further includes a virtual segmentation subsystem that is associated with the protocol data unit receiver subsystem and is configured to perform virtual segmentation on the protocol data unit.

Abstract: A function interface system for use with a fast pattern processor having an internal function bus and an external function bus and a method of operating the same. In one embodiment, the function interface system includes a controller arbitration subsystem configured to process an issued function request received from at least one of the internal function bus and the external function bus and a dispatch subsystem configured to retrieve the issued function request and dispatch the issued function request to at least one associated co-processor via the controller arbitration subsystem.

Abstract: A multi-protocol bus system and a method of operating the same. In one embodiment, the multi-protocol bus system includes a plurality of protocol indicators associated with an address space, each of the plurality of protocol indicators associated with a segment of the address space and configured to indicate a particular bus protocol. The multi-protocol bus system further includes a bus protocol selection subsystem configured to employ control lines to implement one of the particular bus protocols in accordance with a selected one of the protocol indicators based upon an addressed segment of the address space.

Abstract: A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.

Abstract: An apparatus and method for moving and/or resizing logical buffers that comprise a memory space without the loss of data. Each buffer comprises a linear and contiguous set of storage locations, and operates according to a FIFO priority scheme, using a read address pointer to indicate the location from which data is read from the buffer and a write address pointer indicating the address into which data is written. A buffer is relocated or resized within the memory space by changing the base location address (defining the lowest storage location comprising the buffer) and/or the top location address (defining the highest memory location within the buffer) into free storage locations. To accomplish this relocation or resizing without the loss of data, the read address is first checked to determine if it bears an appropriate relationship to the new base and top memory locations.

Abstract: A processing system comprises processing circuitry and memory circuitry coupled to the processing circuitry. The memory circuitry is configurable to maintain at least one queue structure representing a list of data units (e.g., pointers to packets stored in a packet memory). The queue structure is partitioned into two or more blocks (e.g., chunks) wherein at least some of the blocks of the queue structure include two or more data units. Further, at least some of the blocks of the queue structure may include a pointer to a next block of the queue structure (e.g., a next chunk pointer). Given such a queue structure, the processing circuitry is configurable to address a first block of the queue structure, and then address a next block of the queue structure by setting the next block pointer of the first block to point to the next block.

Abstract: A peripheral connectable to a processing device includes a housing and network interface circuitry at least partially enclosed within the housing, the network interface circuitry being utilizable by the processing device to establish a connection between the processing device and a network. The peripheral further includes peripheral circuitry disposed within the housing and adapted to perform at least a portion of at least one of an input function and an output function for the processing device in a manner unrelated to utilization of the network interface circuitry by the processing device. In an illustrative embodiment, the network interface circuitry comprises a wireless local area network (LAN) interface card, module or access point, the processing device comprises a computer, and the peripheral comprises a keyboard, monitor, speaker, docking station or other peripheral connectable to the computer.

Abstract: A processor architecture including a processor and local memory arrangement where the local memory may be accessed by the processor and other resources at substantially the same time. As a result, the processor may initiate a new or current process following a previous process without waiting for data or instructions from external resources. In addition, the loading of data for the next or subsequent process, the execution of a current process, and the extraction of results of a previous process can occur in parallel. Further, the processor may avoid memory load stall conditions because the processor does not have to access an external memory to execute the current process. In another embodiment, the local memory may be dynamically reallocated so that results from a previous process stored in the local memory may be accessed by the processor for a current process without accessing an external memory.

Abstract: A system and method for memory management in a high-speed network environment. Multiple packets are interleaved in data streams and sent to a Memory Manager System. Read and write requests are queued in FIFO buffers. Subsets of these requests are grouped and ordered to optimize processing. This method employs a special arbitration scheme between read and write accesses. Read and write requests are treated as atomic. Memory bank selection is optimized for the request being processed. Alternating between memory bank sets is done to minimize bank conflicts. Link list updates are pipelined. Multiple independent link lists may be supported with the inclusion of a link list identifier. Arbitration between read and write requests continues until the group is exhausted. Then, processing is repeated for the next requests in the BRAM (buffer memories).

Abstract: A biased arbitration technique utilizes a transpose table to arbitrate access to a shared resource. Each column of transpose table is a binary bias vector encoding a bias value assigned to one of the requestors. The rows of the table are fetched to assure that requestors having high bias values are granted more frequent access to the shared resource. A look-ahead feature skips rows having all zeros and an unbiased cycle that assures all requesting ports are serviced regardless of their bias values.

Abstract: A processor includes scheduling circuitry and a priority computation element associated with the scheduling circuitry. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, in accordance with a transmission priority established by the priority computation element. The priority computation element, which may be implemented as a script processor, is operative to determine a transmission priority for one or more constituent transmission elements in a specified group of such transmission elements. The group of transmission elements corresponds to a first level of an n-level hierarchy of transmission elements, with the constituent transmission elements corresponding to at least one lower level of the n-level hierarchy of transmission elements. The transmission priority is preferably made adjustable under software control so as to facilitate the maintenance of a desired service level for one or more of the transmission elements.

Abstract: A processor includes scheduling circuitry for scheduling data blocks for transmission from multiple transmission elements, and traffic shaping circuitry coupled to the scheduling circuitry and operative to establish a traffic shaping requirement for the transmission of the data blocks from the transmission elements. The scheduling circuitry is configured for utilization of at least one time slot table which includes multiple locations, each corresponding to a transmission time slot. The scheduling circuitry is operative in conjunction with the time slot table to schedule the data blocks for transmission in a manner that substantially maintains the traffic shaping requirement established by the traffic shaping circuitry even in the presence of collisions between requests from the transmission elements for each of one or more of the time slots.

Abstract: A processor includes scheduling circuitry for scheduling data blocks for transmission from a plurality of transmission elements. The scheduling circuitry has at least one time slot table accessible thereto, and is configured for utilization of the time slot table in scheduling the data blocks for transmission. The time slot table includes a plurality of locations, with each of the locations corresponding to a transmission time slot and being configurable for storing identifiers of at least two of the transmission elements. In an illustrative embodiment, a given one of the locations in the time slot table stores in a first portion thereof an identifier of a first one of the transmission elements that has requested transmission of a block of data in the corresponding time slot, and stores in a second portion thereof an identifier of a second one of the transmission elements that has requested transmission of a block of data in the corresponding time slot.

Abstract: A processor includes scheduling circuitry and an associated interval computation element. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, and is configured for utilization of at least one time slot table in scheduling the data blocks for transmission. The interval computation element, which may be implemented as a script processor, is operative to determine an interval for transmission of one or more data blocks associated with corresponding locations in the time slot table. The transmission interval is adjustable under control of the interval computation element so as to facilitate the maintenance of a desired service level for one or more of the transmission elements.

Abstract: A processing system comprises processing circuitry and memory circuitry coupled to the processing circuitry. The memory circuitry is configurable to maintain at least one queue structure representing a list of data units (e.g., pointers to packets stored in a packet memory). The queue structure is partitioned into two or more blocks (e.g., chunks) wherein at least some of the blocks of the queue structure include two or more data units. Further, at least some of the blocks of the queue structure may include a pointer to a next block of the queue structure (e.g., a next chunk pointer). Given such a queue structure, the processing circuitry is configurable to address a first block of the queue structure, and then address a next block of the queue structure by setting the next block pointer of the first block to point to the next block.