Patents by Inventor David R. Cheriton

David R. Cheriton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9547533
    Abstract: Improved utilization of connections that can be either available or blocked is provided by associating an atemporal connection state with each connection. If a connection is available, messages are transmitted on the connection normally. If a connection is blocked, the atemporal connection state is updated to reflect the changes that were made but not transmitted. In this manner, a record is kept that allows correct transmission of the information when the connection comes back up. More specifically, after a connection status changes from blocked to available, recovery messages are automatically generated from the atemporal connection state and transmitted on the connection.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: January 17, 2017
    Assignee: Optum Soft, Inc.
    Inventors: David R. Cheriton, Hugh W. Holbrook
  • Patent number: 9520193
    Abstract: Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: December 13, 2016
    Assignee: Intel Corporation
    Inventor: David R. Cheriton
  • Patent number: 9502139
    Abstract: An error in a physical memory realization at a physical memory address is detected. A first physical memory line corresponding to the physical memory address is determined. It is ensured that a duplicate of data content associated with the first physical memory line is associated with a second physical memory line. The physical memory address is remapped to use the second physical memory line for data content.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventor: David R. Cheriton
  • Patent number: 9501421
    Abstract: Memory management includes maintaining a plurality of physical pages corresponding to a respective plurality of indirect lines, where each of the plurality of indirect lines corresponds to a set of one or more data lines. Memory management further includes receiving a request to create a new physical page; determining whether there is an existing physical page that has matching content to the new physical page; and in the event that there is an existing physical page that has matching content as the new physical page, associating the new physical page with the same data lines as those corresponding to the matching content referenced by the indirect line associated with the existing physical page.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventor: David R. Cheriton
  • Patent number: 9477558
    Abstract: Logging changes to a physical memory region during a logging time interval includes: detecting a write operation to the physical memory region, wherein the write operation modifies an indirect representation that corresponds to a physical data line in the physical memory region; and recording log information associated with the write operation.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventor: David R. Cheriton
  • Publication number: 20160292212
    Abstract: Efficient processing of concurrent atomic transactions is provided by identifying the constraints that need to be satisfied for correct application behavior. With these constraints identified, commit processing for a transaction can then refer to the constraints to see if committing the current transaction causes a problem with the constraints. If there is a conflict with the constraints, the transaction aborts. If there is no conflict with the constraints, the transaction commits.
    Type: Application
    Filed: March 11, 2016
    Publication date: October 6, 2016
    Inventor: David R. Cheriton
  • Publication number: 20160291891
    Abstract: Providing data security includes: in response to a request to write data content to a storage, generating encrypted data content based on the data content; attempting to obtain a reference to the encrypted data content in the storage; in the event that the reference to the encrypted data content is obtained, modifying a translation line to refer to the reference to the encrypted data content in the storage; and in the event that the reference to the encrypted data content is not obtained: storing the encrypted data content at a new location; obtaining a reference to the encrypted data content stored at the new location; and modifying the translation line to refer to the reference to the encrypted data content stored at the new location.
    Type: Application
    Filed: January 13, 2015
    Publication date: October 6, 2016
    Applicant: Intel Corporation
    Inventor: David R. Cheriton
  • Patent number: 9411563
    Abstract: A method is provided for translating sets of constraint declarations to imperative code sequences based on defining an instantiatable object per set, inserting calls to a notification callback mechanism on state modification and defining calls in the constraint context as imperative code sequences that, in response to these callbacks, take actions to maintain these constraints.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: August 9, 2016
    Assignee: OptumSoft, Inc.
    Inventor: David R. Cheriton
  • Publication number: 20160224261
    Abstract: A memory controller is used to receive a first request for a portion of a physical memory and metadata associated with the portion of the physical memory. The first request for the portion of the physical memory is translated to correspond to an indirect data structure. The indirect data structure comprises a reference to a data line, and a metadata associated with the data line. The data line is formed within the physical memory.
    Type: Application
    Filed: October 11, 2015
    Publication date: August 4, 2016
    Applicant: Intel Corporation
    Inventors: David R. Cheriton, Alexandre Y. Solomatnikov
  • Publication number: 20160124729
    Abstract: Simplified handling of dynamic collections having a variable number of elements at run time is achieved by providing for specification of collective properties of dynamic collections by a programmer. Such collective properties are distinct from type-member properties of the collection that follow from the types and type qualifiers of its members. Preferably, such dynamic collections are attributes (i.e., members) of an application defined type.
    Type: Application
    Filed: September 1, 2015
    Publication date: May 5, 2016
    Inventor: David R. Cheriton
  • Patent number: 9317549
    Abstract: Efficient processing of concurrent atomic transactions is provided by identifying the constraints that need to be satisfied for correct application behavior. With these constraints identified, commit processing for a transaction can then refer to the constraints to see if committing the current transaction causes a problem with the constraints. If there is a conflict with the constraints, the transaction aborts. If there is no conflict with the constraints, the transaction commits.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: April 19, 2016
    Assignee: OptumSoft, Inc.
    Inventor: David R. Cheriton
  • Patent number: 9274948
    Abstract: A method for managing memory, comprising: maintaining a strong reference count for a first object; establishing a first reference from the first object to a second object; establishing a second reference from the second object to the first object, wherein the second reference is a weak reference that does not increase the strong reference count of the first object; detecting that the strong reference count of the first object has reached zero; in response to detecting that the strong reference count has reached zero, invoking a corresponding action.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: March 1, 2016
    Inventor: David R. Cheriton
  • Patent number: 9262135
    Abstract: A programming language is extended to have embedded interpretive types (EIT) that define objects and variables to be resolved at translation time. A variable or data element having a type that is one of the EITs is referred to as an embedded interpretive variable (EIV). A control construct containing an EIV is interpreted (i.e. executed) at translation time.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: February 16, 2016
    Assignee: OptumSoft, Inc.
    Inventor: David R. Cheriton
  • Patent number: 9208082
    Abstract: A memory controller is used to receive a first request for a portion of a physical memory and metadata associated with the portion of the physical memory. The first request for the portion of the physical memory is translated to correspond to an indirect data structure. The indirect data structure comprises a reference to a data line, and a metadata associated with the data line. The data line is formed within the physical memory.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: December 8, 2015
    Inventor: David R. Cheriton
  • Patent number: 9158519
    Abstract: Simplified handling of dynamic collections having a variable number of elements at run time is achieved by providing for specification of collective properties of dynamic collections by a programmer. Such collective properties are distinct from type-member properties of the collection that follow from the types and type qualifiers of its members. Preferably, such dynamic collections are attributes (i.e., members) of an application defined type.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: October 13, 2015
    Assignee: OptumSoft, Inc.
    Inventor: David R. Cheriton
  • Publication number: 20150261670
    Abstract: Memory reclamation includes executing a process that has a plurality of objects, the objects being accessible via a plurality of references, at least some of the plurality of references being transient references, at least some of the plurality of references being persistent references; reaching a reclamation point at which a process state has no transient references, or has transient references only at known locations; and at the reclamation point, destructing objects that have no persistent references and no transient references.
    Type: Application
    Filed: March 6, 2015
    Publication date: September 17, 2015
    Inventor: David R. Cheriton
  • Patent number: 9111013
    Abstract: A system and method for efficiently searching long strings of data, such as network messages, is described. The system preferably includes an associative memory structure, having a plurality of content addressable memories (CAMs). The CAMs are hierarchically arranged such the output of at least one CAM is used as the input to a second CAM. Preferably, a top-level CAM receives only a selected portion of the data string or network message as its input. The output of the top-level CAM is then joined with some or all of the remaining portions of the data string to form a new output that is provided to the CAM at the next lower level. The top-level CAM is programmed such that its output is substantially smaller (e.g., has fewer bits) than the selected data string portion that is input to the top-level CAM. The system can thus search data strings that are on the whole far longer than the widths of the respective CAMs forming the memory structure.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: August 18, 2015
    Assignee: Cisco Technology, Inc.
    Inventor: David R. Cheriton
  • Patent number: 9047334
    Abstract: Atomically updating an in-memory data structure that is directly accessible by a processor includes comparing old information associated with an old version of the in-memory data structure with current information associated with a current version of the in-memory data structure; in the event that the old information and the current information are the same, replacing the old version with a new version of the in-memory data structure; in the event that the old information and the current information are not the same, determining a difference between the current version of the in-memory data structure and the new version of the in-memory data structure, and determining whether the difference is logically consistent; and in the event that the difference is logically consistent, merging a change in the current version with the new version.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: June 2, 2015
    Assignee: David R. Cheriton
    Inventor: David R. Cheriton
  • Publication number: 20150074339
    Abstract: Accessing a hybrid memory using a translation line is disclosed. The hybrid memory comprises a first portion. The translation line maps a first physical memory address to a first line in the first portion. Said mapping provides an indication that the first line is not immediately accessible in the first portion.
    Type: Application
    Filed: September 8, 2014
    Publication date: March 12, 2015
    Inventor: David R. Cheriton
  • Patent number: 8972950
    Abstract: A method is provided for translating sets of constraint declarations to imperative code sequences based on defining an instantiatable object per set, inserting calls to a notification callback mechanism on state modification and defining calls in the constraint context as imperative code sequences that, in response to these callbacks, take actions to maintain these constraints. This notification and callback mechanism can also be employed in connection with external events, thereby providing for efficient implementation of event-sequenced imperative procedures in a constraint programming language.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: March 3, 2015
    Assignee: OptumSoft, Inc.
    Inventor: David R. Cheriton