Abstract: Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.

Abstract: A programming language is extended to have embedded interpretive types (EIT) that define objects and variables to be resolved at translation time. A variable or data element having a type that is one of the EITs is referred to as an embedded interpretive variable (EIV). A control construct containing an EIV is interpreted (i.e. executed) at translation time.

Abstract: Efficient processing of concurrent atomic transactions is provided by identifying the constraints that need to be satisfied for correct application behavior. With these constraints identified, commit processing for a transaction can then refer to the constraints to see if committing the current transaction causes a problem with the constraints. If there is a conflict with the constraints, the transaction aborts. If there is no conflict with the constraints, the transaction commits.

Abstract: A method is provided for translating sets of constraint declarations to imperative code sequences based on defining an instantiatable object per set, inserting calls to a notification callback mechanism on state modification and defining calls in the constraint context as imperative code sequences that, in response to these callbacks, take actions to maintain these constraints.

Abstract: A method is provided for translating sets of constraint declarations to imperative code sequences based on defining an instantiatable object per set, inserting calls to a notification callback mechanism on state modification and defining calls in the constraint context as imperative code sequences that, in response to these callbacks, take actions to maintain these constraints.

Abstract: A method for managing memory, comprising: maintaining a strong reference count for a first object; establishing a first reference from the first object to a second object; establishing a second reference from the second object to the first object, wherein the second reference is a weak reference that does not increase the strong reference count of the first object; detecting that the strong reference count of the first object has reached zero; in response to detecting that the strong reference count has reached zero, invoking a corresponding action.

Abstract: A method for providing security groups based on the use of tunneling is disclosed. The method includes assigning a security group identifier (SGI) to a packet and classifying the packet based on the packet's SGI.

Abstract: Providing a snapshot of a physical memory region as of a specified time includes: sending, from a first processor to a second processor, a request to generate a snapshot of the physical memory region as of the specified time; and generating, using the second processor, the snapshot of the physical memory region based at least in part on a known state of the physical memory region and log information about update activity of the physical memory region.

Abstract: Logging changes to a physical memory region during a logging time interval includes: detecting a write operation to the physical memory region, wherein the write operation modifies an indirect representation that corresponds to a physical data line in the physical memory region; and recording log information associated with the write operation.

Abstract: A programming language is extended to have embedded interpretive types (EIT) that define objects and variables to be resolved at translation time. A variable or data element having a type that is one of the EITs is referred to as an embedded interpretive variable (EIV). A control construct containing an EIV is interpreted (i.e. executed) at translation time.

Abstract: Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.

Abstract: Improved utilization of connections that can be either available or blocked is provided by associating an atemporal connection state with each connection. If a connection is available, messages are transmitted on the connection normally. If a connection is blocked, the atemporal connection state is updated to reflect the changes that were made but not transmitted. In this manner, a record is kept that allows correct transmission of the information when the connection comes back up. More specifically, after a connection status changes from blocked to available, recovery messages are automatically generated from the atemporal connection state and transmitted on the connection.

Abstract: Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.

Abstract: Memory access for accessing a memory subsystem is disclosed. An instruction is received to access a memory location through a register. A tag is detected in the register, the tag being configured to indicate which memory path to access. On the event that the tag is configured to indicate that a first memory path is used, the memory subsystem is accessed via the first memory path. In the event that the tag is configured to indicate that a second memory path is used, the memory subsystem is accessed via the second memory path.

Abstract: Intercepting a requested memory operation corresponding to a conventional memory is disclosed. The requested memory operation is translated to be applied to a structured memory.

Abstract: A system includes a network tunnel, an ingress network device coupled to send packets via the network tunnel, and an egress network device coupled to receive packets sent via the network tunnel. The egress network device is configured to provide information to the ingress network device. The information indicates whether a packet transmitted from the ingress network device to the egress network device was dropped in the network tunnel. The ingress network device can retransmit the packet to the egress network device if the packet is dropped in the network tunnel.

Abstract: A method and apparatus for determining if a packet is a duplicate packet are disclosed. The method includes determining if a field of a duplicate packet map (DPM) indicates the packet is the duplicate packet. The determination is made using a packet summary value (PSV) corresponding to the packet. The apparatus (a network device, for example) includes a duplicate packet map (DPM), which can be used to make the foregoing determination.

Abstract: Intercepting a requested memory operation corresponding to a conventional memory is disclosed. The requested memory operation is translated to be applied to a structured memory.

Abstract: The invention provides an enhanced datagram packet switched computer network. The invention processes network datagram packets in network devices as separate flows, based on the source-destination address pair in the datagram packet. As a result, the network can control and manage each flow of datagrams in a segregated fashion. The processing steps that can be specified for each flow include traffic management, flow control, packet forwarding, access control, and other network management functions. The ability to control network traffic on a per flow basis allows for the efficient handling of a wide range and a large variety of network traffic, as is typical in large-scale computer networks, including video and multimedia traffic. The amount of buffer resources and bandwidth resources assigned to each flow can be individually controlled by network management. In the dynamic operation of the network, these resources can be varied—based on actual network traffic loading and congestion encountered.

Abstract: Data transmission efficiency for structured data can be improved by representing structured data using immutable blocks. The contents of the immutable blocks can include data and/or pointers to immutable blocks. An immutable data block cannot be altered after creation of the block. When data represented as immutable blocks is transmitted from one processor to another processor, the transmitter sends block contents for blocks that have not previously been defined at the receiver, and sends block IDs (as opposed to block contents) for blocks that have previously been defined at the receiver. The systematic use of block IDs instead of block contents in transmission where possible can significantly reduce transmission bandwidth requirements.