Abstract: A circuit can include a capacitor that has a semiconductor layer, a dielectric layer, and a conductive layer. The circuit can include an insulating layer and a metal or conductive layer. The metal layer can have a first portion that has a first plurality of fingers, and a second portion that has a second plurality of fingers, which can be interdigitated with the first plurality of fingers. The circuit can include one or more first electrical connections that electrically couple the first portion of the metal layer to the semiconductor layer of the capacitor. The circuit can include one or more second electrical connections that electrically couple the second portion of the metal layer to the conductive layer of the capacitor. A capacitance provided by the interdigitated first and second pluralities of fingers can be at least about 3% of a capacitance provided by the capacitor.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly. The source fingers and the drain fingers can be arranged in alternating rows.

Abstract: Silicon-on-insulator (SOI) substrate processing for transistor enhancement is disclosed. In certain embodiments, a silicon substrate for an SOI process is separated into sub-regions or islands by dielectric. Thus, the substrate is changed from having one region and one shared contact into multiple substrate sub-regions with independent contacts. Since the substrate serves as a back gate to SOI transistors formed in an active silicon layer, breaking the substrate into independent or separate islands leads to a drop in the impact of each island on the drain-to-source voltage and/or gate-to-source voltage of the SOI transistors. Accordingly, reduced harmonics and improved linearity are achieved.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: A field-effect transistor (FET) and a radio-frequency module are provided comprising an active region comprising a source region, a drain region, a body region disposed between the source region and the drain region, a first body extension portion in contact with the body region, a second body extension portion in contact with the body region, and a body contact region in contact with the first extension portion and the second extension portion; and a gate disposed on a top surface of the body region. A die is also provided comprising two or more such FETs.

Abstract: Apparatus and methods for distributing millimeter wave cellular service over a face of a building are disclosed. In certain embodiments, an antenna assembly includes an antenna upper unit configured to extend from a top of a building, such as from a roof. The antenna upper unit includes a first linear antenna array that radiates a transmit beam having a disc-shaped pattern. The antenna assembly includes an antenna lower unit configured to extend from the building beneath the antenna upper unit. The antenna lower unit includes a second linear antenna array that receives the transmit beam.

Abstract: Antenna arrays with multiple feeds and varying pitch are disclosed. In certain embodiments, a radio frequency (RF) module includes a module substrate, a semiconductor die attached to the module substrate, and an antenna array attached to the module substrate. The semiconductor die includes a plurality of power amplifiers configured to amplify a corresponding plurality of RF signals to generate a plurality of amplified RF signals. The antenna array is configured to receive the plurality of amplified RF signals from the plurality of power amplifiers, and includes a plurality of antenna elements arranged with a varying pitch. Each of the plurality of antenna elements includes two or more signal feeds.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: SOI-based technology platforms are described that provide fully integrated front end integrated circuits (FEICs) that include switches, low-noise amplifiers (LNAs), and power amplifiers (PAs). The PAs can be built in a thick film region of the integrated circuit, resulting in a partially depleted silicon-on-insulator (PDSOI) PA, and the switches and LNAs can be built in a thin film region of the integrated circuit, resulting in fully depleted silicon-on-insulator (FDSOI) switches and LNAs. The resulting fully integrated FEIC includes PDSOI PAs with FDSOI switches and LNAs. Passive components can be built in the thick film region, the thin film region, or both regions.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly. The source fingers and the drain fingers can be arranged in alternating rows.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly.

Abstract: A method for fabricating a semiconductor device involves providing a transistor device formed over an oxide layer formed on a semiconductor substrate, removing at least part of the semiconductor substrate, applying an interface material below to at least a portion of the oxide layer, removing a portion of the interface material to form a trench, and at least partially covering the interface material and the trench with a substrate layer to form a cavity.

Abstract: A semiconductor device includes a transistor implemented over an oxide layer, one or more electrical connections to the transistor, one or more dielectric layers formed over at least a portion of the electrical connections, an electrical element disposed over the one or more dielectric layers, the electrical element being in electrical communication with the transistor via the one or more electrical connections, a patterned form of sacrificial material covering at least a portion of the electrical element, and an interface layer covering at least a portion of the one or more dielectric layers and the sacrificial material.

Abstract: Radio-frequency core circuitry includes a first switch arm associated with a first signal band and coupled to a common node, a second switch arm associated with a second signal band and coupled to the common node, a first shunt arm connected to a first shunt node in the first switch arm, and a first transmission line disposed in the first switch arm between the common node and the shunt node and having a length configured present an open circuit at a fundamental frequency associated with the second signal band and to present a short circuit at a harmonic of the fundamental frequency associated with the second signal band.

Abstract: A transistor device includes a plurality of drain fingers that are elongate in a first dimension, a plurality of source fingers that are elongate in the first dimension and interleaved with the plurality of drain fingers, one or more drain contact bars extending over a first set of the plurality of drain fingers and a first set of the plurality of source fingers in a second dimension that is orthogonal to the first dimension, and one or more source contact bars extending over a second set of the plurality of drain fingers and a second set of the plurality of source fingers in the second dimension.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.