Patents by Inventor David Theodore Blaauw
David Theodore Blaauw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11024624Abstract: In a particular implementation, an apparatus to control clamping devices includes a first control circuit and a second control circuit. The first control circuit is responsive to a detection signal and generates a first drive signal to control a body diode of a clamping device. The second control circuit is responsive to the detection signal and generates a second drive signal to control the gate terminal of the clamping device.Type: GrantFiled: July 24, 2018Date of Patent: June 1, 2021Assignees: Arm Limited, The Regents of the University of MichiganInventors: Parameshwarappa Anand Kumar Savanth, Fabrice Blanc, David Theodore Blaauw, Sechang Oh, In Hee Lee
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Patent number: 10579463Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.Type: GrantFiled: September 9, 2016Date of Patent: March 3, 2020Assignees: ARM Limited, The Regents of the University of MichiganInventors: Krisztian Flautner, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge, David Bull
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Patent number: 10572334Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.Type: GrantFiled: October 12, 2015Date of Patent: February 25, 2020Assignees: ARM Limited, The Regents of the University of MichiganInventors: Krisztian Flautner, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge, David Bull
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Publication number: 20200035668Abstract: In a particular implementation, an apparatus to control clamping devices includes a first control circuit and a second control circuit. The first control circuit is responsive to a detection signal and generates a first drive signal to control a body diode of a clamping device. The second control circuit is responsive to the detection signal and generates a second drive signal to control the gate terminal of the clamping device.Type: ApplicationFiled: July 24, 2018Publication date: January 30, 2020Inventors: Parameshwarappa Anand Kumar Savanth, Fabrice Blanc, David Theodore Blaauw, Sechang Oh, In Hee Lee
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Patent number: 10476382Abstract: Various implementations described herein are directed to a device having a charge pump and a capacitor. The charge pump may be configured for coupling between first and second power sources. The capacitor may be configured for coupling between the first power source and an input of the charge pump. In an energy harvest mode, the charge pump may decouple from the first and second power sources, and the first power source may charge the capacitor with a first voltage while the charge pump is decoupled from the first and second power sources. In an energy transfer mode, the charge pump may couple to the capacitor and the second power source to transfer the first voltage from the capacitor to the second power source during discharge of the first voltage from the capacitor.Type: GrantFiled: March 3, 2016Date of Patent: November 12, 2019Assignee: The Regents of the University of MichiganInventors: Xiao Wu, David Theodore Blaauw, Dennis Michael Chen Sylvester
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Patent number: 10409615Abstract: Subject matter disclosed herein may relate to arithmetic units of processors, and may relate more particularly to configurable arithmetic units. Configurable arithmetic units may comprise a plurality of basic units, and may further comprise a programmable fabric to selectively connect the plurality of basic units at least in part to process one or more sets of parameters in accordance with one or more specified arithmetic operations.Type: GrantFiled: June 19, 2017Date of Patent: September 10, 2019Assignee: The Regents of the University of MichiganInventors: Yajing Chen, Trevor Mudge, Ronald Dreslinski, Jr., Shengshuo Lu, Hun Seok Kim, David Theodore Blaauw, Fu Cheng
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Patent number: 10326449Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include clock circuitry having a first plurality of logic components arranged to receive a low voltage supply, a data input signal and a clock input signal and to provide a first plurality of intermediate signals and multiple intermediate clock signals. The integrated circuit may include level converter core circuitry having voltage biasing circuitry and voltage control circuitry arranged to receive a high voltage supply, the first plurality of intermediate signals and the multiple intermediate clock signals and to provide a second plurality of intermediate signals. The integrated circuit may include latch circuitry having a second plurality of logic components arranged to receive the high voltage supply, the low voltage supply and the second plurality of intermediate signals and to provide a data output signal.Type: GrantFiled: October 6, 2017Date of Patent: June 18, 2019Assignee: The Regents of the University of MichiganInventors: Jeongsup Lee, Mehdi Saligane, David Theodore Blaauw, Dennis Michael Chen Sylvester
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Publication number: 20190109588Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include clock circuitry having a first plurality of logic components arranged to receive a low voltage supply, a data input signal and a clock input signal and to provide a first plurality of intermediate signals and multiple intermediate clock signals. The integrated circuit may include level converter core circuitry having voltage biasing circuitry and voltage control circuitry arranged to receive a high voltage supply, the first plurality of intermediate signals and the multiple intermediate clock signals and to provide a second plurality of intermediate signals. The integrated circuit may include latch circuitry having a second plurality of logic components arranged to receive the high voltage supply, the low voltage supply and the second plurality of intermediate signals and to provide a data output signal.Type: ApplicationFiled: October 6, 2017Publication date: April 11, 2019Inventors: Jeongsup Lee, Mehdi Saligane, David Theodore Blaauw, Dennis Michael Chen Sylvester
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Patent number: 10181788Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first voltage source providing a first voltage having a first polarity. The integrated circuit may include a second voltage source providing a second voltage having a second polarity that is opposite the first polarity. The integrated circuit may include a first circuit portion configured to receive the first and second voltages and provide one or more feedback voltages. The integrated circuit may include a second circuit portion configured to receive the first and second voltages along with the one or more feedback voltages and provide an output voltage that is proportional to the first voltage based on a rational conversion ratio that is derived by selection of at least one of the first and second voltages and the one or more feedback voltages.Type: GrantFiled: January 29, 2016Date of Patent: January 15, 2019Assignee: The Regents of the University of MichiganInventors: Wanyeong Jung, Dennis Michael Chen Sylvester, David Theodore Blaauw
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Publication number: 20180365021Abstract: Subject matter disclosed herein may relate to arithmetic units of processors, and may relate more particularly to configurable arithmetic units. Configurable arithmetic units may comprise a plurality of basic units, and may further comprise a programmable fabric to selectively connect the plurality of basic units at least in part to process one or more sets of parameters in accordance with one or more specified arithmetic operations.Type: ApplicationFiled: June 19, 2017Publication date: December 20, 2018Inventors: Yajing Chen, Trevor Mudge, Ronald Dreslinski, JR., Shengshuo Lu, Hun Seok Kim, David Theodore Blaauw, Fu Cheng
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Patent number: 10056121Abstract: Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.Type: GrantFiled: March 6, 2017Date of Patent: August 21, 2018Assignees: ARM Limited, The Regents of the University of MichiganInventors: Mahmood Khayatzadeh, Massimo Bruno Alioto, David Theodore Blaauw, Dennis Michael Chen Sylvester, Fakhruddin Ali Bohra
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Patent number: 10037295Abstract: An interconnect within an integrated circuit provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).Type: GrantFiled: December 2, 2016Date of Patent: July 31, 2018Assignee: The Regents of the University of MichiganInventors: Supreet Jeloka, Sandunmalee Nilmini Abeyratne, Ronald George Dreslinski, Reetuparna Das, Trevor Nigel Mudge, David Theodore Blaauw
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Patent number: 9966954Abstract: Physically Unclonable Function (PUF) cells are described, suitable for CMOS technology, where each PUF cell is based upon a two-transistor amplifier design. A PUF cell includes a voltage generator followed by one or more amplifier stages. Also described is a method and apparatus for determining a dark bit mask for an array of PUF cells based on the two-transistor amplifier design.Type: GrantFiled: February 3, 2017Date of Patent: May 8, 2018Assignee: The Regents of the University of MichiganInventors: Kaiyuan Yang, David Theodore Blaauw, Dennis Michael Chen Sylvester
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Patent number: 9800143Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a charge pump stage having multiple charge storage elements arranged to provide multiple sets of voltages in alternating phases. The integrated circuit may include a voltage multiplexing stage having multiple multiplexers arranged to receive the multiple sets of voltages in the alternating phases. Each multiplexer may provide a selected voltage from the multiple sets of voltages based on a conversion ratio. The integrated circuit may include a voltage summing stage having multiple sampling charge storage elements arranged to receive the selected voltages from each multiplexer and provide an output voltage as a sum of the selected voltages received from each multiplexer.Type: GrantFiled: September 9, 2016Date of Patent: October 24, 2017Assignee: The Regents of the University of MichiganInventors: Xiao Wu, David Theodore Blaauw, Dennis Michael Chen Sylvester
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Publication number: 20170257023Abstract: Various implementations described herein are directed to a device having a charge pump and a capacitor. The charge pump may be configured for coupling between first and second power sources. The capacitor may be configured for coupling between the first power source and an input of the charge pump. In an energy harvest mode, the charge pump may decouple from the first and second power sources, and the first power source may charge the capacitor with a first voltage while the charge pump is decoupled from the first and second power sources. In an energy transfer mode, the charge pump may couple to the capacitor and the second power source to transfer the first voltage from the capacitor to the second power source during discharge of the first voltage from the capacitor.Type: ApplicationFiled: March 3, 2016Publication date: September 7, 2017Inventors: Xiao Wu, David Theodore Blaauw, Dennis Michael Chen Sylvester
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Publication number: 20170257024Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a charge pump stage having multiple charge storage elements arranged to provide multiple sets of voltages in alternating phases. The integrated circuit may include a voltage multiplexing stage having multiple multiplexers arranged to receive the multiple sets of voltages in the alternating phases. Each multiplexer may provide a selected voltage from the multiple sets of voltages based on a conversion ratio. The integrated circuit may include a voltage summing stage having multiple sampling charge storage elements arranged to receive the selected voltages from each multiplexer and provide an output voltage as a sum of the selected voltages received from each multiplexer.Type: ApplicationFiled: September 9, 2016Publication date: September 7, 2017Inventors: Xiao Wu, David Theodore Blaauw, Dennis Michael Chen Sylvester
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Publication number: 20170222538Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first voltage source providing a first voltage having a first polarity. The integrated circuit may include a second voltage source providing a second voltage having a second polarity that is opposite the first polarity. The integrated circuit may include a first circuit portion configured to receive the first and second voltages and provide one or more feedback voltages. The integrated circuit may include a second circuit portion configured to receive the first and second voltages along with the one or more feedback voltages and provide an output voltage that is proportional to the first voltage based on a rational conversion ratio that is derived by selection of at least one of the first and second voltages and the one or more feedback voltages.Type: ApplicationFiled: January 29, 2016Publication date: August 3, 2017Inventors: Wanyeong Jung, Dennis Michael Chen Sylvester, David Theodore Blaauw
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Publication number: 20170178700Abstract: Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.Type: ApplicationFiled: March 6, 2017Publication date: June 22, 2017Inventors: Mahmood Khayatzadeh, Massimo Bruno Alioto, David Theodore Blaauw, Dennis Michael Chen Sylvester, Fakhruddin Ali Bohra
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Patent number: 9638752Abstract: A measurement circuit and method are provided for measuring a clock node to output node delay of a flip-flop. A main ring oscillator has a plurality of main unit cells arranged in a ring, with each main unit cell comprising a flip-flop and pulse generation circuitry connected to the output node of the flip-flop. The flip-flop is responsive to receipt of an input clock pulse at the clock node to output a data value transition from the output node, and the pulse generation circuitry then generates from the data value transition an input clock pulse for a next main unit cell in the main ring, whereby the main ring oscillator generates a first output signal having a first oscillation period.Type: GrantFiled: February 7, 2014Date of Patent: May 2, 2017Assignees: ARM Limited, The Regents of the University of MichiganInventors: Yejoong Kim, Dennis Michael Sylvester, David Theodore Blaauw, Brian Tracy Cline
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Patent number: 9635147Abstract: A protocol for transmitting data from an external device to an electronic device is provided in which the external device transmits a data stream which includes the same data packet repeated multiple times. The data packet has a predetermined length and has a header portion at a predetermined position. A receiver at the electronic device captures a block of data having the predetermined length from the transmitted data stream, and a decoder rotates the captured block of data to place the header portion at the predetermined position within the data packet. This eliminates the need for an accurate jitter-free clock reference at the electronic device. By shifting power consumption and system complexity to the external unit where power is typically not constrained, the energy efficiency of the electronic device can be increased.Type: GrantFiled: July 9, 2014Date of Patent: April 25, 2017Assignee: The Regents of the University of MichiganInventors: Mohammad Hassan Ghaed, Skylar Skrzyniarz, David Theodore Blaauw, Dennis Michael Sylvester