Abstract: An interconnect within an integrated circuit provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).

Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Abstract: An interconnect within an integrated circuit provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).

Abstract: Oscillator regulation circuitry is provided for regulating a frequency of an output signal generated by an oscillator. Oscillator regulation circuitry has frequency sensing circuitry for sensing the frequency of the output signal and generating a first signal depending on the frequency, and control circuitry which generates the oscillator control signal based on the comparison between the first signal and a non-oscillating reference signal. The frequency sensing circuitry includes at least one switched capacitor. This approach provides improved noise reduction, less sensitivity to process, temperature and voltage variations, and a more linear scaling of the frequency with the reference signal, compared to previous techniques.

Abstract: Synchronisation circuitry 2 comprises a first dynamic circuit stage 4 generating a first stage state signal which is pulse amplified by pulse amplifying circuitry 8 to generate a pulse amplified signal. The pulse amplified signal is supplied to a second dynamic circuit stage 6 where it is used to control generation of a second stage state signal. The pulse amplifying circuitry 8 comprises a chain of serially connected skewed inverters 20, 22. The action of the pulse amplifying circuitry 8 is to reduce the probability of metastability in the output of the second dynamic stage 6.

Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Abstract: An electronic device has an energy storage device and circuitry supplied with a storage device voltage from the energy storage device. A supervisor circuit enables the circuitry in response to the storage device exceeding an enable threshold voltage. The supervisor circuit detects a resistance parameter which is indicative of an internal resistance of the energy storage device and adjusts the enable threshold voltage based on the resistance parameter.

Abstract: A storage device has a plurality of storage cells for storing data values. Control circuitry is provided to simultaneously couple at least two cells to at least one common signal line. Sensing circuitry is provided to sense a signal on the at least one common signal line, which indicates a result of a logical operation applied to the data values stored in each of the at least two storage cells. This allows logic operations such as AND, OR, XOR, etc. to be performed within a storage device so that it is not necessary to read out each data value independently and transfer each data value to a separate processing circuit in order to find the result of the logical operation. This helps to improve performance within a data processing apparatus having the storage device.

Abstract: A storage device has a plurality of storage cells for storing data values. Control circuitry is provided to simultaneously couple at least two cells to at least one common signal line. Sensing circuitry is provided to sense a signal on the at least one common signal line, which indicates a result of a logical operation applied to the data values stored in each of the at least two storage cells. This allows logic operations such as AND, OR, XOR, etc. to be performed within a storage device so that it is not necessary to read out each data value independently and transfer each data value to a separate processing circuit in order to find the result of the logical operation. This helps to improve performance within a data processing apparatus having the storage device.

Abstract: Oscillator regulation circuitry is provided for regulating a frequency of an output signal generated by an oscillator. Oscillator regulation circuitry has frequency sensing circuitry for sensing the frequency of the output signal and generating a first signal depending on the frequency, and control circuitry which generates the oscillator control signal based on the comparison between the first signal and a non-oscillating reference signal. The frequency sensing circuitry includes at least one switched capacitor. This approach provides improved noise reduction, less sensitivity to process, temperature and voltage variations, and a more linear scaling of the frequency with the reference signal, compared to previous techniques.

Abstract: A true random number generator comprises a ring oscillator which is triggered to start oscillating in a first mode of oscillation at an oscillation start time. The first mode of oscillation will eventually collapse to a second mode of oscillation dependent on thermal noise. A collapse time from the oscillation start time to the time at which the oscillator collapses to the second mode is measured, and this can be used to determine a random number. The TRNG can be synthesized entirely using standard digital techniques and is able to provide high randomness, good throughput and energy efficiency.

Abstract: Memory circuitry 2 includes an array 4 of bit cells 6. One or more boost capacitors C1, C2 are connected to bit lines 8 running through the array 4 and serve to store a sample charge with a sample voltage difference during a sampling configuration of the boost capacitors C1, C2. A boost configuration is subsequently adopted in which the boost capacitors C1, C2 are connected with a different plurality to respective bit lines 8 such that the sample voltage difference is added to the voltage change within the bit line produced by the bit line cell 6 so as to generate an increased magnitude change in voltage which is supplied to sense amplifier circuitry 12.

Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Abstract: A protocol for transmitting data from an external device to an electronic device is provided in which the external device transmits a data stream which includes the same data packet repeated multiple times. The data packet has a predetermined length and has a header portion at a predetermined position. A receiver at the electronic device captures a block of data having the predetermined length from the transmitted data stream, and a decoder rotates the captured block of data to place the header portion at the predetermined position within the data packet. This eliminates the need for an accurate jitter-free clock reference at the electronic device. By shifting power consumption and system complexity to the external unit where power is typically not constrained, the energy efficiency of the electronic device can be increased.

Abstract: Circuitry formed of a two-dimensional regular array of capacitive elements 2 is coupled to decoding circuitry in the form of column decoder 8 and a row decoder 6. The decoders 8, 6 are used to select a start point and an end point within a sequence of selected capacitive elements to be connected in parallel following a horizontal raster scan arrangement. The selected capacitive elements may be used to generate an output voltage with a magnitude corresponding to the number of selected capacitive elements.

Abstract: An electronic device has an energy storage device and circuitry supplied with a storage device voltage from the energy storage device. A supervisor circuit enables the circuitry in response to the storage device exceeding an enable threshold voltage. The supervisor circuit detects a resistance parameter which is indicative of an internal resistance of the energy storage device and adjusts the enable threshold voltage based on the resistance parameter.

Abstract: Circuitry formed of a two-dimensional regular array of capacitive elements 2 is coupled to decoding circuitry in the form of column decoder 8 and a row decoder 6. The decoders 8, 6 are used to select a start point and an end point within a sequence of selected capacitive elements to be connected in parallel following a horizontal raster scan arrangement. The selected capacitive elements may be used to generate an output voltage with a magnitude corresponding to the number of selected capacitive elements.

Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Abstract: A measurement circuit and method are provided for measuring a clock node to output node delay of a flip-flop. A main ring oscillator has a plurality of main unit cells arranged in a ring, with each main unit cell comprising a flip-flop and pulse generation circuitry connected to the output node of the flip-flop. The flip-flop is responsive to receipt of an input clock pulse at the clock node to output a data value transition from the output node, and the pulse generation circuitry then generates from the data value transition an input clock pulse for a next main unit cell in the main ring, whereby the main ring oscillator generates a first output signal having a first oscillation period.

Abstract: A level conversion circuit has a keeper circuit for retaining an intermediate output node at a high output level to avoid it floating due to leakage through a pullup transistor in a shifting circuit. Thin oxide and thick oxide versions of the level conversion circuit can be provided. The level conversion circuit enables higher performance, reduced power consumption and reduced susceptibility to process variation compared to previous level conversion designs.