Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.

Abstract: There is provided an integrated circuit comprising:

Abstract: There is provided a memory for storing data comprising:

Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 2, a non-delayed latch 4, a delayed latch 8 and a comparator 6. The non-delayed latch 4 captures an output from the processing logic 2 at a non-delayed capture time. At a later delayed capture time, the delayed latch 8 also captures a value from the processing logic 2. The comparator 6 compares these values and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock.

Abstract: A process and implementing computer system (13) for updating circuit representations in a hierarchical Directed Acyclic Graph (DAG) format (400-410) based upon changes made to the primitive components of the circuit in a flat representation (201-213) includes performing a depth first search (505) on the hierarchical representation of the circuit beginning at the root level (501) for a given path. At each lower level, each child instance is visited (505) and if there is any change in any attribute between the hierarchical and flat representations (509), the component in the hierarchical representation which needs to be changed is copied (807) and connected to the children components of the original hierarchical representation. Changes in the attributes of the children components are made in the copied component (809).