Patents by Inventor David Wei Wang

David Wei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190146953
    Abstract: The concepts relate to data handling, and more specifically to data handling scenarios where data is revised on one computer and stored on another computer. One example can obtain a set of blobs relating to revisions of a file. The example can determine a target size of datastore blobs. In an instance where a total size of the set of blobs is less than the target size, this example can aggregate the set of blobs into an individual datastore blob. Otherwise, the example can identify new or edited individual blobs of the set and aggregate the new or edited individual blobs into first datastore blobs. The example can also aggregate other individual blobs of the set into second datastore blobs.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 16, 2019
    Inventors: Mitesh Pankaj PATEL, Miko Arnab Sakhya Singha BOSE, Simon Peter CLARKE, David OLIVER, Andrew WATSON, Ming-wei WANG, Steven RAYSON
  • Patent number: 9307676
    Abstract: A thermally enhanced electronic package comprises a driver chip, an insulator, a flexible carrier, and carbon nanocapsules. The flexible carrier includes a flexible substrate, a wiring layer formed on the substrate, and a resistant overlaying the wiring layer. The driver chip is connected to the wiring layer. The insulator is filled in the gap between the driver chip and the flexible carrier. The carbon nanocapsules are disposed on the driver chip, on the resistant, on the flexible carrier, or in the insulator to enhance heat dissipation of electronic packages.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: April 5, 2016
    Assignee: CHIPMOS TECHNOLOGIES INC.
    Inventors: Tzu Hsin Huang, Yu Ting Yang, Hung Hsin Liu, An Hong Liu, Geng Shin Shen, David Wei Wang, Shih Fu Lee
  • Patent number: 8752635
    Abstract: A technique is provided that utilizes one or both of a control line actuation mechanism and a connector protection mechanism for use in a wellbore environment. Upon landing a lower well assembly and an upper well assembly at a desired wellbore location, control line connectors are engaged. The control line actuation mechanism and/or connector protection mechanism facilitate the formation of a desirable control line connection.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: June 17, 2014
    Assignee: Schlumberger Technology Corporation
    Inventors: David Wei Wang, Michael Hui Du, Gary L. Rytlewski, David Verzwyvelt
  • Patent number: 8635392
    Abstract: A layer management interface (LMI) to communicate with a processor over MDIO protocol, and to communicate with a media access control security (MACsec) functional block over a local network protocol, the LMI including a command register to receive command information for transacting data information with the destination portion within the MACsec, an address register to receive address information associated with the destination portion without conducting all the MDIO address cycles required by the MDIO protocol to receive the address information, the LMI being configured to determine a location of the destination portion based on the received address information, and a data register to transact the data information without conducting all MDIO data cycles required by the MDIO protocol to transact the data information, and to transact the data information with the determined destination portion based on the command information over the local network protocol.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: January 21, 2014
    Assignee: Broadcom Corporation
    Inventor: David (Wei) Wang
  • Publication number: 20130294033
    Abstract: A thermally enhanced electronic package comprises a driver chip, an insulator, a flexible carrier, and carbon nanocapsules. The flexible carrier includes a flexible substrate, a wiring layer formed on the substrate, and a resistant overlaying the wiring layer. The driver chip is connected to the wiring layer. The insulator is filled in the gap between the driver chip and the flexible carrier. The carbon nanocapsules are disposed on the driver chip, on the resistant, on the flexible carrier, or in the insulator to enhance heat dissipation of electronic packages.
    Type: Application
    Filed: July 5, 2013
    Publication date: November 7, 2013
    Inventors: TZU HSIN HUANG, YU TING YANG, HUNG HSIN LIU, AN HONG LIU, GENG SHIN SHEN, DAVID WEI WANG, SHIH FU LEE
  • Patent number: 8469109
    Abstract: An apparatus and method for plugging a wellbore completion. The apparatus includes a body and a variable diameter ring. The body includes a first portion having a first diameter, and a second portion having a second diameter that is smaller than the first diameter. The variable diameter ring is disposed around the body and slidable on the first and second portions. The ring is configured to engage a flow path reduction device when located on the first portion, and to move past the flow path reduction device when located on the second portion.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: June 25, 2013
    Assignee: Schlumberger Technology Corporation
    Inventors: David Wei Wang, Gary L. Rytlewski
  • Publication number: 20130119530
    Abstract: A thermally enhanced packaging structure includes a chip carrier; a high power chip disposed on the chip carrier; a molding compound covering the high power chip; a heat dissipating layer disposed on the molding compound, wherein the heat dissipating layer comprises a plurality of carbon nanocapsules (CNCs); and a non-fin type heat dissipating device, disposed either on the heat dissipating layer or between the molding compound and the heat dissipating layer. The molding compound can also comprise a plurality of CNCs.
    Type: Application
    Filed: August 17, 2012
    Publication date: May 16, 2013
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventors: AN HONG LIU, David Wei Wang, Shi Fen Huang, Yi Chang Lee, Hsiang Ming Huang
  • Patent number: 8338935
    Abstract: A thermally enhanced electronic package comprises a chip, a substrate, an adhesive, and an encapsulation. The adhesive or the encapsulation is mixed with carbon nanocapsules. The substrate includes an insulation layer and a wiring layer formed on the substrate. The adhesive covers the chip and the substrate. The chip is electrically connected to the wiring layer. The encapsulation covers the chip and the substrate.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: December 25, 2012
    Assignee: Chipmos Technologies Inc.
    Inventors: An Hong Liu, David Wei Wang
  • Publication number: 20120299036
    Abstract: A thermally enhanced light emitting device package includes a substrate, a chip attached to the substrate, an encapsulant overlaid on the chip, and a plurality of non-electrically conductive carbon nanocapsules mixed in the encapsulant to facilitate heat dissipation from the chip.
    Type: Application
    Filed: May 26, 2011
    Publication date: November 29, 2012
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventors: AN HONG LIU, RUENN BO TSAI, DAVID WEI WANG
  • Patent number: 8269352
    Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: September 18, 2012
    Assignee: Chipmos Technologies Inc.
    Inventors: David Wei Wang, An-Hong Liu, Hsiang-Ming Huang, Jar-Dar Yang, Yi-Chang Lee
  • Patent number: 8269351
    Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: September 18, 2012
    Assignee: Chipmos Technologies Inc.
    Inventors: David Wei Wang, An-Hong Liu, Hsiang-Ming Huang, Jar-Dar Yang, Yi-Chang Lee
  • Patent number: 8264068
    Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: September 11, 2012
    Assignee: Chipmos Technologies Inc.
    Inventors: David Wei Wang, An-Hong Liu, Hsiang-Ming Huang, Jar-Dar Yang, Yi-Chang Lee
  • Patent number: 8220533
    Abstract: According to one or more aspects of the present disclosure, a piezoelectric pump may include a hydraulic fluid path between a low pressure source and a high pressure tool port; a fluid disposed in the hydraulic fluid path; a piston in communication with the fluid; and a piezoelectric material connected to the piston to pump the fluid through the high pressure tool port.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: July 17, 2012
    Assignee: Schlumberger Technology Corporation
    Inventors: Colin Longfield, David Wei Wang, Gary L. Rytlewski
  • Patent number: 8195247
    Abstract: Certain embodiments of a cable sense mode for intelligent power saving in the absence of a link pulse may include detecting an energy level of an Ethernet link. The Ethernet link may couple a network adapter chip to a network. The power supplied to the network adapter chip may be adjusted based on the detected energy level. Power may be supplied to the network adapter chip if the detected energy level of the Ethernet link is greater than or equal to a particular energy level. Power may be reduced to the network adapter chip if the detected energy level of the Ethernet link is less than a particular energy level. An output signal and/or an interrupt signal may be generated that indicates a change in the detected energy level of the Ethernet link. Power may be provided to the circuitry that generates the output signal and the interrupt signal.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: June 5, 2012
    Assignee: Broadcom Corporation
    Inventors: Jonathan F. Lee, Gregory Youngblood, David (Wei) Wang
  • Publication number: 20110309495
    Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.
    Type: Application
    Filed: January 12, 2011
    Publication date: December 22, 2011
    Inventors: David Wei Wang, An-Hong Liu, Hsiang-Ming Huang, Jar-Dar Yang, Yi-Chang Lee
  • Publication number: 20110309497
    Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.
    Type: Application
    Filed: January 12, 2011
    Publication date: December 22, 2011
    Inventors: David Wei WANG, An-Hong Liu, Hsiang-Ming Huang, Jar-Dar Yang, Yi-Chang Lee
  • Publication number: 20110309496
    Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.
    Type: Application
    Filed: January 12, 2011
    Publication date: December 22, 2011
    Inventors: David Wei WANG, An-Hong Liu, Hsiang-Ming Huang, Jar-Dar Yang, Yi-Chang Lee
  • Publication number: 20110304045
    Abstract: A thermally enhanced electronic package comprises a chip, a substrate, an adhesive, and an encapsulation. The adhesive or the encapsulation is mixed with carbon nanocapsules. The substrate includes an insulation layer and a wiring layer formed on the substrate. The adhesive covers the chip and the substrate. The chip is electrically connected to the wiring layer. The encapsulation covers the chip and the substrate.
    Type: Application
    Filed: May 26, 2011
    Publication date: December 15, 2011
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventors: AN HONG LIU, DAVID WEI WANG
  • Publication number: 20110304991
    Abstract: A thermally enhanced electronic package comprises a driver chip, an insulator, a flexible carrier, and carbon nanocapsules. The flexible carrier includes a flexible substrate, a wiring layer formed on the substrate, and a resistant overlaying the wiring layer. The driver chip is connected to the wiring layer. The insulator is filled in the gap between the driver chip and the flexible carrier. The carbon nanocapsules are disposed on the driver chip, on the resistant, on the flexible carrier, or in the insulator to enhance heat dissipation of electronic packages.
    Type: Application
    Filed: November 18, 2010
    Publication date: December 15, 2011
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventors: TZU HSIN HUANG, YU TING YANG, HUNG HSIN LIU, AN HONG LIU, GENG SHIN SHEN, DAVID WEI WANG, SHIH FU LEE
  • Publication number: 20110291267
    Abstract: A semiconductor wafer structure comprises a first surface and a second surface opposite to the first surface, a plurality of chip areas formed on the first surface, a plurality of through-silicon holes formed in each of the plurality of chip areas connecting the first surface and the second surface, and a through-silicon-via (TSV) electrode structure formed in each through-silicon hole. Each through-silicon-via electrode structure comprises a dielectric layer formed on the inner wall of the through-silicon hole, a barrier layer formed on the inner wall of the dielectric layer and defining a vacancy therein, a filling metal layer filled into the vacancy, a first end of the filling metal layer being lower than the first surface forming a recess, and a soft metal cap connecting to and overlaying the first end of the filling metal layer, wherein a portion of the soft metal cap is formed in the recess and the soft metal cap protrudes out of the first surface.
    Type: Application
    Filed: August 16, 2010
    Publication date: December 1, 2011
    Inventors: David Wei Wang, An-Hong Liu, Hsiang-Ming Huang, Yi-Chang Lee