Patents by Inventor David White

David White has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150069808
    Abstract: A seat assembly is provided for supporting in an automotive vehicle. The seat assembly comprises a seat cushion and a seat back pivotally coupled to the seat cushion for movement between a reclined seating position and a fold flat position. A recliner assembly is coupled between the seat back and the seat cushion to provide pivotal movement of the seat back. A riser assembly is pivotally coupled to the seat cushion and pivotally latched to the floor to allow pivotal movement of the seat cushion between a horizontal seating position and a forwardly upright tumbled position. A release mechanism is coupled between the seat back and the riser assembly for automatically synchronizing actuation of the recliner assembly and the riser assembly to provide movement of the seat assembly to the tumbled position in response to the pivotal movement of the seat back to the fold flat position.
    Type: Application
    Filed: September 19, 2014
    Publication date: March 12, 2015
    Inventors: David A White, Prasad D. Jagtap, Alan Proulx, Timothy J. Brush, Jeffrey P. Carroll, Omar D. Tame, Robert T. Coffey, Rabindranath Persad, Douglas A. Dingel, Nelson E. Hurst, Jerzy Dzledzic, Lei Cao, Brian Adwell
  • Patent number: 8973059
    Abstract: The present invention concerns an apparatus for protecting a satellite reception system from strong terrestrial signals. A high Q tunable trap is used to help reject strong ATSC signals or other signals that may be present on the input coaxial cable of a satellite receiver that operates in a single-wire multi-switch (SWM) environment.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: March 3, 2015
    Assignee: Thomson Licensing
    Inventors: David White, Henri Girard
  • Patent number: 8898617
    Abstract: The present invention allows for a robust design using manufacturability models. A method, system and/or computer usable medium may be provided in an integrated circuit design to track sensitivity to a variation of process from wafer to wafer and/or fab to fab in order to assist the designers to anticipate the variations to improve the final yield of the products.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: November 25, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: David White, Louis K. Scheffer
  • Patent number: 8864209
    Abstract: A seat assembly is provided for supporting in an automotive vehicle. The seat assembly comprises a seat cushion and a seat back pivotally coupled to the seat cushion for movement between a reclined seating position and a fold flat position. A recliner assembly is coupled between the seat back and the seat cushion to provide pivotal movement of the seat back. A riser assembly is pivotally coupled to the seat cushion and pivotally latched to the floor to allow pivotal movement of the seat cushion between a horizontal seating position and a forwardly upright tumbled position. A release mechanism is coupled between the seat back and the riser assembly for automatically synchronizing actuation of the recliner assembly and the riser assembly to provide movement of the seat assembly to the tumbled position in response to the pivotal movement of the seat back to the fold flat position.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: October 21, 2014
    Assignee: Magna Seating Inc.
    Inventors: David A. White, Prasad D. Jagtap, Alan Proulx, Timothy Jon Brush, Jeffrey P. Carroll, Omar D Tame, Robert Thomas Coffey, Rabindranath Persad, Douglas A Dingel, Nelson E Hurst, Jerzy Dziedzic, Lei Cao, Brian Adwell
  • Patent number: 8850755
    Abstract: Provided herein are solar collectors having reflective sheets which are slidably insertable and/or removable for quick installation, construction, removal, repair, and/or replacement. Also provided are solar collectors having reflective sheets under tension. Further provided are methods for constructing solar collectors. In another aspect, provided herein are guide rails for guiding and/or retaining slidably removable reflective sheets and holding the reflective sheets in a prescribed shape.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: October 7, 2014
    Assignee: Skyfuel, Inc.
    Inventors: Randall C. Gee, Scott Audette, Randolph Carl Brost, Adrian L. Farr, Robert Hawkins, David White, Shannon Thomson
  • Publication number: 20140290069
    Abstract: The device is used to slice, store, display or transport cakes. It is primarily composed of four elements; a cutter, a holder, an alignment tray and a holder tray which combine for performing various features of the invention. The device is useful for birthdays, general storage, restaurants or parties.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Inventor: David White, III
  • Patent number: 8844949
    Abstract: A collapsible shopping cart includes a collapsible support assembly having a support frame with a vertical frame member and a horizontal frame member. The vertical support member is pivotally secured to the horizontal support member allowing the support frame to be selectively folded. A plurality of wheels are coupled to the horizontal support member. The plurality of wheels are coupled to the horizontal support member for movement between a use orientation and a storage orientation, wherein when the plurality of wheels are in the use orientation they extend from the horizontal support member in a manner permitting engagement with a horizontal support surface such that the support assembly may roll thereupon. First and second storage receptacles shaped and dimensioned for selective attachment to the support assembly are provided.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: September 30, 2014
    Assignee: Cargo Cart Co.
    Inventors: Allison White, David White, Matthew A. Sommerfield
  • Publication number: 20140251313
    Abstract: Provided are reflective thin film constructions including a reduced number of layers, which provides for increased solar-weighted hemispherical reflectance and durability. Reflective films include those comprising an ultraviolet absorbing abrasion resistant coating over a metal layer. Also provided are ultraviolet absorbing abrasion resistant coatings and methods for optimizing the ultraviolet absorption of an abrasion resistant coating. Reflective films disclosed herein are useful for solar reflecting, solar collecting, and solar concentrating applications, such as for the generation of electrical power.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: SkyFuel, Inc
    Inventors: Gary JORGENSEN, Randall C. GEE, David WHITE
  • Publication number: 20140237440
    Abstract: Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment.
    Type: Application
    Filed: April 7, 2014
    Publication date: August 21, 2014
    Applicant: Cadence Design Systems, Inc.
    Inventors: Prakash Gopalakrishnan, Michael McSherry, David White, Ed Fischer, Bruce Yanagida, Keith Dennison
  • Publication number: 20140223906
    Abstract: Solar/gas hybrid concentrating solar power (CSP) systems and methods of using the CSP systems are described. The hybrid CSP systems are highly efficient due, at least in part, to a solar segment comprising a first heat transfer fluid and a thermal storage segment comprising a second heat transfer fluid. The second heat transfer fluid heat exchanges with a steam segment to produce steam that drives a steam turbine. Thus, the solar and thermal segments perform the “heavy lifting” of producing steam from water. Once the steam is produced, it enters a superheater of the steam segment. The superheater, which does not heat exchange directly with the thermal storage segment, is heated by a gas turbine positioned downstream from the thermal storage segment.
    Type: Application
    Filed: February 8, 2013
    Publication date: August 14, 2014
    Inventors: Randall C. GEE, David WHITE
  • Publication number: 20140219535
    Abstract: In one embodiment, the presence of anomalous material within tissue is detected by scanning a patient using magnetic resonance imaging (MRI) to obtain MRI data, identifying individual voxels of the MRI data, identifying multiple parameters of each voxel, and determining as to each voxel based upon the identified parameters the likelihood of tissue represented by the voxel containing anomalous material.
    Type: Application
    Filed: September 6, 2012
    Publication date: August 7, 2014
    Inventors: Yunmei Chen, Mark Rogers Davidson, Keith David White, Jon Paul Dobson
  • Patent number: 8782577
    Abstract: Disclosed are a method, system, and computer program product for providing customizable information in designing electronic circuits with electrical awareness. The method or the system displays a portion of a physical design of an electronic circuit in a first display area. The method or the system receives or identifies a user's or a system's manipulation of the portion of the physical design of the electronic circuit. The method or the system then determines and displays an in situ response to the manipulation in the first display area. The method or the system may further display, in the first display area or in another display area, result(s) relating to the physical data of a component, electrical parasitic(s) associated with the physical data, electrical characteristic(s) associated with the physical data or the electrical characteristic(s), or other element(s) of the physical design that is impacted by the manipulation.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: July 15, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ed Fischer, David White, Michael McSherry, Bruce Yanagida, Vance Kenzle
  • Patent number: 8772330
    Abstract: The present disclosure concerns a compound, or a pharmaceutically acceptable salt thereof, having a formula: where at least one of R1-R4 is a heterocycle, at least one of R1-R4 is an aryl group coupled to the ring by a linker atom, functional group, or other moiety, or where none of R1-R4 is an amide, and any and all combinations thereof. Remaining R1-R4 substituents independently are aliphatic, substituted aliphatic, amine, substituted amine, aryl, substituted aryl, cyclic, substituted cyclic, halide, heteroaryl, substituted heteroaryl, heterocyclic, substituted heterocyclic, hydrogen or hydroxyl. A method for treating a subject also is provided comprising administering a disclosed compound or compounds, or a prodrug that is converted into the disclosed compound or compounds, or a composition comprising the compound, compounds, or prodrugs thereof, to a subject. A method for making disclosed compounds also is provided.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: July 8, 2014
    Assignee: State of Oregon acting by and through the State Board of Higher Education on behalf of Oregon State University
    Inventors: James David White, David T. Wong, David B. Chan, Jongtae Yang, Rajan Juniku
  • Patent number: 8769453
    Abstract: Disclosed is an improved method, system, and computer program product for preparing multiple levels of semiconductor substrates for three-dimensional IC integration. Some embodiments utilize the process and design models to check and fabricate the insulating dielectric layer (IDL) separating the first and the second film stacks on separate substrates and then prepare the surface of the IDL to receive an additional layer of semiconductor substrate for further fabrication of the chips. Yet some other embodiments further employ the design and process models to ensure the IDL and the semiconductor substrate are sufficiently flat, or are otherwise satisfactory, so the three-dimensional integrated circuits meet the reliability, manufacturability, yield, or performance requirements. Yet some other embodiments further employ design and process models to place the vias connecting the multiple film stacks.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: July 1, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Louis K. Scheffer, David White
  • Patent number: 8762914
    Abstract: Disclosed are methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness. Some embodiments identify or set parasitic constraint(s) and compare the electrical parasitic(s) with corresponding parasitic constraint(s) to determine whether the parasitic constraints are met. Some embodiments first identify, determine, or update the physical data of a component of a partial layout and characterize the electrical parasitics associated with the physical data of the component. Some embodiments identify or determine some schematic level performance constraints and estimate parasitic constraints based on schematic simulation results and the performance constraints; the estimated parasitic constraints are then compared with the corresponding electrical parasitics to determine whether the constraints are satisfied.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: June 24, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ed Fischer, Michael McSherry, David White, Bruce Yanagida, Akshat Shah
  • Patent number: 8701067
    Abstract: Disclosed are a method, system, and computer program product for implementing electronic circuit designs with IR-drop awareness. Some embodiments perform schematic level simulation(s) to determine electrical characteristics, identifies physical parasitics of a layout component, determines the electrical or physical characteristics associated to IR-drop analysis on the component, and determines whether the component meets IR-drop related constraint(s) while implementing the physical design of the electronic circuit in some embodiments. Some embodiments further determine adjustment(s) to the component or related data where the IR-drop related constraints are not met and/or and present the adjustment(s) in the form of hints. Various data and information, such as currents in various forms or voltages, are passed between various schematic level tools and physical level tools.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: April 15, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Michael McSherry, Bruce Yanagida, Ed Fischer, David White, Prakash Krishnan
  • Patent number: 8694950
    Abstract: Disclosed are a method, system, and computer program product for implementing electronic circuit designs with electrical awareness. The method or the system updates the schematic level tool(s) and physical design tool(s) with electrical parasitic data or electrical characteristic data associated with electrical parasitics so both schematic and physical design tools are aware of the electrical parasitic or characteristic data in performing their functions such as extraction based simulations. The methods or systems are also aware of EM or IR-drop constraint(s) while implementing or creating a partial layout less than a complete layout. The method or the system also provides a user interface for a design tool to provide in situ, customizable, real-time information for implementing electronic circuit designs with electrical awareness. The methods or systems also support constraint verification for electronic circuit design implementation with electrical awareness.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: April 8, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Michael McSherry, David White, Ed Fischer, Bruce Yanagida, Prakash Gopalakrishnan, Keith Dennison, Akshat Shah
  • Patent number: 8694933
    Abstract: Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: April 8, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Prakash Gopalakrishnan, Michael McSherry, David White, Ed Fischer, Bruce Yanagida, Keith Dennison
  • Patent number: 8689169
    Abstract: Disclosed are a method, system, and computer program product for providing customizable information in designing electronic circuits with electrical awareness. The method or the system displays a portion of a physical design of an electronic circuit in a first display area. The method or the system receives or identifies a user's or a system's manipulation of the portion of the physical design of the electronic circuit. The method or the system then determines and displays an in situ response to the manipulation in the first display area. The method or the system may further display, in the first display area or in another display area, result(s) relating to the physical data of a component, electrical parasitic(s) associated with the physical data, electrical characteristic(s) associated with the physical data or the electrical characteristic(s), or other element(s) of the physical design that is impacted by the manipulation.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: April 1, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ed Fischer, David White, Michael McSherry, Bruce Yanagida
  • Patent number: D701571
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: March 25, 2014
    Assignee: Dallas Lighthouse for the Blind
    Inventors: Nancy Perkins, Gordon Spark, David White, Jonathan Kirkpatrick, Ian White, Ian McDermott