Abstract: A method for manufacturing a semiconductor structure is provided. The method may include several operations. A substrate is provided, received or formed, wherein the substrate includes an epitaxial structure in a fin structure of the substrate and a metal gate structure over the fin structure. An insulating layer covering the metal gate structure is formed. A semiconductive material layer is formed over the epitaxial structure and the insulating layer, wherein a first portion of the semiconductive material layer over the epitaxial structure comprises crystalline semiconductive material, and a second portion of the semiconductive material layer over the insulating layer comprises amorphous semiconductive material. The second portion of the semiconductive material layer is removed. A semiconductor structure thereof is also provided.

Abstract: In various examples, a yield scenario may be identified for a first vehicle. A wait element is received that encodes a first path for the first vehicle to traverse a yield area and a second path for a second vehicle to traverse the yield area. The first path is employed to determine a first trajectory in the yield area for the first vehicle based at least on a first location of the first vehicle at a time and the second path is employed to determine a second trajectory in the yield area for the second vehicle based at least on a second location of the second vehicle at the time. To operate the first vehicle in accordance with a wait state, it may be determined whether there is a conflict between the first trajectory and the second trajectory, where the wait state defines a yielding behavior for the first vehicle.

Abstract: An apparatus and method of blind detection of binauralized audio. If the input content is detected as binaural, a second binauralization may be avoided. In this manner, the user experience avoids audio artifacts introduced by multiple binauralizations.

Abstract: In various examples, sensor data recorded in the real-world may be leveraged to generate transformed, additional, sensor data to test one or more functions of a vehicle—such as a function of an AEB, CMW, LDW, ALC, or ACC system. Sensor data recorded by the sensors may be augmented, transformed, or otherwise updated to represent sensor data corresponding to state information defined by a simulation test profile for testing the vehicle function(s). Once a set of test data has been generated, the test data may be processed by a system of the vehicle to determine the efficacy of the system with respect to any number of test criteria. As a result, a test set including additional or alternative instances of sensor data may be generated from real-world recorded sensor data to test a vehicle in a variety of test scenarios—including those that may be too dangerous to test in the real-world.

Abstract: Lease-based consistency may be implemented for databases to handle failovers. A database node may obtain a consistency lease that describes a point in time determined from a time-to-live amount added to a consistent point in time for database data. While the consistency lease is valid, Multi-version Concurrency Control (MVCC) snapshots assigned by the database node can be used to handle requests to access the database data. Once expired, the database node may have to renew the consistency lease in order to continue to handle write and read requests.

Abstract: The present disclosure relates to processes, methods, systems, and apparatus for steam cracking hydrocarbon in a pyrolysis furnace having a convection zone and a radiant zone. The convection zone includes three heat exchangers in series with a serpentine arrangement. A fluid source is disposed each heat exchanger to provide steam into the heat exchangers. The present disclosure further relates to a process of adjusting the stream flow rate for each fluid source to control operating conditions such as flue gas temperature, stack temperatures, and temperatures of other components of the furnace.

Abstract: A method for forming a semiconductor structure is provided. A structure including a sacrificial spacer interposed between a metal gate structure and a dielectric structure is received. A temperature of the sacrificial spacer is increased. At least a portion of the sacrificial spacer is removed to form a recess between the metal gate structure and the dielectric structure. A spacer is formed in the recess along a sidewall of the metal gate structure. A semiconductor structure is also provided.

Abstract: The present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer.

Abstract: Systems and methods for creating a reorganization-immune blockchain index using mono-increasing sequence records are described. For example, the system may receive on-chain data for a plurality of blocks, wherein the plurality of blocks comprises a first block comprising a first event of a plurality of blockchain events within the on-chain data. The system may determine a first sequence number for the first event, wherein the first sequence number is based on a mono-increasing sequence record.

Abstract: A culture medium is provided which is capable of establishing expanded potential stem cell (EPSC) lines which resemble naïve or ground state ES cells, but are also able to differentiate into placenta trophoblasts and the embryo proper. Methods are provided using the medium for the in vitro conversion and maintenance of cells, including pluripotent cells into EPSCs.

Abstract: Embodiments of the disclosure relate to an optical fiber ribbon. The optical fiber ribbon includes a plurality of optical fibers arranged adjacently to each other and a plurality of bonding regions intermittently spaced along a length of the optical fiber ribbon. At each bonding region, at least one bond is formed between two optical fibers of the plurality of optical fibers. Further, the at least one bond comprises a first material applied to outer surfaces of the two optical fibers and a second material applied over the first material. The first material is different from the second material, and at least one of the first material or the second material includes a colorant configured to identify the optical fiber ribbon. Also disclosed are embodiments of making such an optical fiber ribbon as well as of optical fiber cables including such an optical fiber ribbon.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.

Abstract: A method for treating a semiconductor structure includes: disposing the semiconductor structure in a chamber; introducing a modifying agent into the chamber to modify a surface part of a dielectric element; and introducing a removing agent into the chamber while applying an electromagnetic radiation with a selected frequency to the chamber so as to permit the dielectric element to be selectively heated by the electromagnetic radiation to have a temperature higher than those of other elements of the semiconductor structure, and so as to permit the modified surface part of the dielectric element to be removed.

Abstract: A semiconductor device includes a channel layer, an interfacial layer, a gate dielectric layer, a gate electrode, dipole elements, and additional elements. The interfacial layer is disposed on the channel layer, and includes an insulating material. The gate dielectric layer is disposed over the interfacial layer such that the channel layer is separated from the gate dielectric layer by the interfacial layer. The gate electrode is disposed on the gate dielectric layer. The dipole elements are present in at least one of the interfacial layer and the gate dielectric layer in a predetermined amount such that the semiconductor device has a predetermined threshold voltage. The additional elements are located at a region where the dipole elements are present so as to reduce interfacial defects caused by the dipole elements. The additional elements are different from the dipole elements. Methods for manufacturing the semiconductor device are also disclosed.

Abstract: A semiconductor device with different configurations of nanostructured channel regions and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a stack of nanostructured horizontal channel (NHC) regions disposed on the fin structure, a nanostructured vertical channel (NVC) region disposed within the stack of NHC regions, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the NHC regions and on portions of the NVC region that are not covered by the NHC regions and the fin structure.

Abstract: The present disclosure describes a method to form a stacked semiconductor device with power rails. The method includes forming the stacked semiconductor device on a first surface of a substrate. The stacked semiconductor device includes a first fin structure, an isolation structure on the first fin structure, and a second fin structure above the first fin structure and in contact with the isolation structure. The first fin structure includes a first source/drain (S/D) region, and the second fin structure includes a second S/D region. The method also includes etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening. The second surface is opposite to the first surface. The method further includes forming a dielectric barrier in the opening and forming an S/D contact in the opening.

Abstract: The present disclosure describes a method to form a stacked semiconductor device with power rails. The method includes forming the stacked semiconductor device on a first surface of a substrate. The stacked semiconductor device includes a first fin structure, an isolation structure on the first fin structure, and a second fin structure above the first fin structure and in contact with the isolation structure. The first fin structure includes a first source/drain (S/D) region, and the second fin structure includes a second S/D region. The method also includes etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening. The second surface is opposite to the first surface. The method further includes forming a dielectric barrier in the opening and forming an S/D contact in the opening.

Abstract: A semiconductor device with different configurations of nanostructured channel regions and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a stack of nanostructured horizontal channel (NHC) regions disposed on the fin structure, a nanostructured vertical channel (NVC) region disposed within the stack of NHC regions, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the NHC regions and on portions of the NVC region that are not covered by the NHC regions and the fin structure.