Abstract: The present invention provides a power factor correction circuit (21, 22), a power factor correction assembly (2) and an on-line uninterruptible power supply including the same. The power factor correction circuit (21) comprises a pulse width modulated rectifier (211, 221) and an isolated DC-DC converter (212, 222), wherein an output of the pulse width modulated rectifier (211, 221) is connected to an input of the isolated DC-DC converter (212, 222). The power factor correction assembly (2) comprises a plurality of power factor correction circuits (21, 22) described above, wherein inputs of pulse width modulated rectifiers (211, 221) in the plurality of power factor correction circuits (21, 22) are connected in series, and outputs of isolated DC-DC converters (212, 222) in the plurality of power factor correction circuits (21, 22) are connected in parallel.

Abstract: The present invention provides an apparatus to actively balance the thermal performance of paralleled power devices, comprising: a monitoring unit for monitoring the temperature of each power device of the paralleled power devices to judge whether the temperature is out of balance; and a balancing unit for adjusting power loss of the power devices with monitored higher temperatures so as to achieve the balance of the thermal performance of the paralleled power devices.

Abstract: A stable control system for a three-phase rectification controller circuit is provided. The stable control system filters voltage harmonics and performs attenuation feedback compensation on current harmonics to enable a rectification circuit to achieve high stability and low THDi, while performing filtering on a direct current bus voltage in the case of an unbalanced load, so as to filter out voltage harmonics and enable the circuit to support the unbalanced load. A stable control system for an interleaved direct current booster circuit is also provided. The stable control system equalizes inter-leg currents such that a battery has good dynamic effects and good current equalization performance.

Abstract: An integrated transmitter chip having a transmitter block, the transmitter block having: a first power divider optically connected to a first input port; a second power divider optically connected to a second input port; a first plurality of optical channels optically branched from the first power divider; a second plurality of optical channels optically branched from the second power divider; a first multiplexer optically connected to a first optical channel of the first plurality of optical channels and a first optical channel of the second plurality of optical channels, and a second multiplexer optically connected to a second optical channel of the first plurality of optical channels and a second optical channel of the second plurality of optical channels. The integrated transmitter chip may be configured to utilize polarization division multiplexing or wavelength division multiplexing to combine optical signals depending on the application of the corresponding integrated transmitter chip.

Abstract: An integrated transmitter chip comprising: at least one input port disposed at a first end of the integrated transmitter chip; a first variable power divider optically connected to each input port of the at least one input port; a second and a third variable power dividers optically branched from each first variable power divider; a first and a second optical channel optically branched from the second variable power divider, a third and a fourth optical channel optically branched from the third variable power divider; and at least one WDM optically attached to corresponding optical channels and configured to selectively modify the polarization of and multiplex corresponding optical signals into a output optical signal, wherein a laser beam is launched into an input port, split by corresponding variable power dividers based upon each dividers corresponding splitting ratio, then multiplexed and combined into an output optical signal having dual polarization modes.

Abstract: The present disclosure provides a multi-input power converter, including three bridge arm units connected between a three-phase alternating current power supply and a positive/negative direct current bus. A first capacitor and a second capacitor are connected in series between the positive direct current bus and the negative direct current bus, and a node formed by connecting the capacitors is connected to a neutral point. Each bridge arm unit includes an inductor and a bidirectional switch unit that are connected in series, and a current direction control bridge arm connected between the positive direct current bus and the negative direct current bus, and a node formed by connecting the inductor to the bidirectional switch unit is connected to the current direction control bridge arm. Second ends of bidirectional switch units of the three bridge arm units are connected to the neutral point.

Abstract: An integrated Mach-Zehnder Interferometer comprising: an upper arm and a lower arm; and a differential thermo-optic phase shifter comprising a first heating element and a second heating element collocated with the upper arm and the lower arm, respectively, the first heating element having a first resistance and the second heating element having a second resistance, an upper pad electrically connected to the first heating element, the upper pad being adapted to receive a first voltage, a lower pad electrically connected to the second heating element, the lower pad being adapted to receive a second voltage, and a common pad electrically connected to the first heating element and the second heating element, the common pad being adapted to receive a third voltage; wherein, when the first, the second, and the third voltages are applied to the upper, the lower, and the common pads, respectively, a phase shift difference is thermally produced.

Abstract: The present invention provides a Miller clamping device for parallel switching transistors and a driver comprising the same. The Miller clamping device includes: a driver chip including an output terminal and a built-in Miller clamping circuit with a Miller clamping terminal, the output terminal of the driver chip being configured to output a pulse width modulation signal; and a plurality of auxiliary Miller clamping circuits, each of the auxiliary Miller clamping circuits being connected between a gate of a corresponding switching transistor and the Miller clamping terminal of the built-in Miller clamping circuit. When the built-in Miller clamping circuit is triggered for Miller clamping, a Miller current generated by the corresponding switching transistor flows to a first direct-current (DC) voltage through a corresponding auxiliary Miller clamping circuit. The Miller clamping device of the present invention can perform Miller clamping on the parallel switching transistors and reduce the circuit cost.

Abstract: The utility model provides a tower UPS frame and a tower UPS. The tower UPS frame comprises: a power supply module frame, which comprises two ports disposed oppositely; a power supply distribution frame; and a fan assembly, which comprises a fan frame and a fan fixed on the fan frame, wherein the power supply distribution frame and the fan frame are arranged in a same row as the power supply module frame and are detachably connected with the two ports of the power supply module frame. The tower UPS frame of the utility model is convenient in assembly and disassembly and reduces repair cost.

Abstract: The present invention provides an uninterruptible power supply with bypass power sharing function, including: an input end, configured to be connected to mains; an output end, configured to be connected to a load; a current sensor, disposed at the output end and configured to sense an output current of the uninterruptible power supply; a bypass branch, disposed between the input end and the output end; and an inverter branch, including a rectifier, an inverter and an energy storage battery, wherein one end of the rectifier is connected to the input end, and the other end is connected to one end of the inverter; the other end of the inverter is connected to the output end; and the energy storage battery is connected to a node between the rectifier and the inverter, wherein the uninterruptible power supply is set to be capable of working in a mains mode; and in the mains mode, the inverter branch is controlled with a current loop, so that the bypass branch and the inverter branch together provide the output cur

Abstract: A silicon photonics based single wavelength 100 Gbit/s PAM4 DWDM transceiver in a pluggable form factor having a transmitter, said transmitter having: a DWDM laser source; a fiber array pigtail having a polarization maintaining fiber and an output single mode fiber; a silicon photonics modulator chip configured to optically connect to the DWDM laser source through the usage of the polarization maintaining fiber, a modulator driver chip connected to the silicon photonics modulator chip and an LC receptacle configured to optically connect to the silicon photonics modulator chip through the usage of the output single mode fiber. The disclosed transmitter may be further comprised of a reference loop within the silicon photonics modulator chip to allow for the utilization of a passive alignment approach for optically connected elements. The disclosed transceiver may be configured for use with C-band DWDM applications for utilization in applicable technologies, including 5G telecommunications.

Abstract: The present invention provides a control system for a three-phase inverter, which comprises an instantaneous value voltage controller and an equivalent effective value voltage controller, wherein the instantaneous value voltage controller is configured to feed back and control an instantaneous value of an inverter output voltage, the equivalent effective value voltage controller is configured to perform an orthogonal decomposition feedback control on an effective value of the inverter output voltage, and wherein the equivalent effective value voltage controller is configured to perform integral compensation respectively on a real-axis voltage and an imaginary-axis voltage of a two-phase rotating coordinate system of the three-phase inverter, and an output of the instantaneous value voltage controller and an output of the equivalent effective value voltage controller are used to obtain the inverter output voltage through a delay stage transfer function and a controlled object transfer function.

Abstract: An integrated waveguide polarizer comprising: a plurality of silicon layers and a plurality of silicon-nitride layers; each of the plurality of silicon layers and each of the plurality of silicon-nitride layers having a first end and an opposite second end, the first end having a wide width and the second end having a narrow width, such that each silicon layer and each silicon-nitride layer have tapered shapes; wherein the pluralities of silicon and silicon-nitride layers are overlapped, such that at least a portion of each silicon-nitride layer overlaps at least a portion of each silicon layer; and a plurality of oxide layers disposed between the pluralities of silicon-nitride and silicon layers, each oxide layer creating a separation spacing between each silicon-nitride and each silicon layers; wherein, when an optical signal is launched through the integrated waveguide polarizer, the optical signal is transitioned between each silicon-nitride layer and each silicon layer.

Abstract: A system for optically aligning a photonics die to a fiber array, the fiber array comprising a first and a second fiber channels, the system comprising: the photonics die having: a first and a second optical channels; a first and a second wavelength division multiplexing (WDM) couplers each comprising a bar port, a cross port, and a common port, the first and the second WDM couplers being optically connected to the first and the second optical channels, respectively, via the bar ports and the common ports; and a waveguide crossing optically connecting the cross ports of the first and the second WDM couplers; the system being adapted to couple an optical signal received from the first fiber channel into the cross port of the first WDM coupler and into the waveguide crossing, the optical signal being propagated from the waveguide crossing into the cross port of the second WDM coupler.

Abstract: An integrated transceiver chip comprising: a plurality of bidirectional ports; a plurality of grating couplers; a receiver having a first and a second input ports, the first input port being optically connected to a first grating coupler of the plurality of grating couplers, and the second input port being optically connected to a first bidirectional port of the plurality of bidirectional ports; and a transmitter having a first and a second input and a first and a second output ports, the first input port being optically connected to a second bidirectional port of the plurality of bidirectional ports and the second input port being optically connected to a second grating coupler, and the first output port being optically connected to a third bidirectional port of the plurality of bidirectional ports and the second output port being optically connected to a third grating coupler of the plurality of grating couplers.

Abstract: An optical apparatus comprising an integrated germanium photodetector associated with a silicon nitride launch waveguide, the integrated germanium photodetector comprising a silicon layer, a germanium layer disposed atop the silicon layer, a plurality of conductive vias, at least one conductive via of the plurality of conductive vias being disposed atop the germanium layer, and a plurality of metal contacts each interconnected to each of the plurality of conductive vias; wherein the silicon nitride launch waveguide extends over a length of the silicon layer, and such that to create a coupling region between the silicon nitride launch waveguide and the germanium layer; and wherein, when an optical signal is launched into the silicon nitride launch waveguide, the optical signal is caused to be coupled into the integrated germanium photodetector at the coupling region, such that to be absorbed by the germanium layer.

Abstract: An integrated transmitter chip comprising: at least one input port disposed at a first end of the integrated transmitter chip; a first variable power divider optically connected to each input port of the at least one input port; a second and a third variable power dividers optically branched from each first variable power divider; a first and a second optical channel optically branched from the second variable power divider, a third and a fourth optical channel optically branched from the third variable power divider; and at least one WDM optically attached to corresponding optical channels and configured to selectively modify the polarization of and multiplex corresponding optical signals into a output optical signal, wherein a laser beam is launched into an input port, split by corresponding variable power dividers based upon each dividers corresponding splitting ratio, then multiplexed and combined into an output optical signal having dual polarization modes.

Abstract: A silicon photonics based single wavelength 100 Gbit/s PAM4 DWDM transceiver in a pluggable form factor having a transmitter, said transmitter having: a DWDM laser source; a fiber array pigtail having a polarization maintaining fiber and an output single mode fiber; a silicon photonics modulator chip configured to optically connect to the DWDM laser source through the usage of the polarization maintaining fiber, a modulator driver chip connected to the silicon photonics modulator chip and an LC receptacle configured to optically connect to the silicon photonics modulator chip through the usage of the output single mode fiber. The disclosed transmitter may be further comprised of a reference loop within the silicon photonics modulator chip to allow for the utilization of a passive alignment approach for optically connected elements. The disclosed transceiver may be configured for use with C-band DWDM applications for utilization in applicable technologies, including 5G telecommunications.

Abstract: An integrated waveguide polarizer comprising: a plurality of silicon layers and a plurality of silicon-nitride layers; each of the plurality of silicon layers and each of the plurality of silicon-nitride layers having a first end and an opposite second end, the first end having a wide width and the second end having a narrow width, such that each silicon layer and each silicon-nitride layer have tapered shapes; wherein the pluralities of silicon and silicon-nitride layers are overlapped, such that at least a portion of each silicon-nitride layer overlaps at least a portion of each silicon layer; and a plurality of oxide layers disposed between the pluralities of silicon-nitride and silicon layers, each oxide layer creating a separation spacing between each silicon-nitride and each silicon layers; wherein, when an optical signal is launched through the integrated waveguide polarizer, the optical signal is transitioned between each silicon-nitride layer and each silicon layer.

Abstract: An integrated photonics chip comprising: a plurality of optical channels extending a length of the integrated photonics chip; at least one variable optical attenuator (VOA) being optically connected to one of the plurality of optical channels, the at least one VOA comprising a silicon diode; at least one modulator being optically connected to another of the plurality of optical channels, the at least one modulator comprising a silicon diode; wherein the silicon diodes of the at least one VOA and the at least one modulator are adapted to receive biasing voltages; and wherein an application of the biasing voltages causes the silicon diodes of the at least one VOA and the at least one modulator to be reverse-biased, such that the at least one VOA and the at least one modulator are each adapted to detect a photocurrent of an optical signal being propagated along the plurality of optical channels.