Abstract: An integrated waveguide polarizer comprising: a plurality of silicon layers and a plurality of silicon-nitride layers; each of the plurality of silicon layers and each of the plurality of silicon-nitride layers having a first end and an opposite second end, the first end having a wide width and the second end having a narrow width, such that each silicon layer and each silicon-nitride layer have tapered shapes; wherein the pluralities of silicon and silicon-nitride layers are overlapped, such that at least a portion of each silicon-nitride layer overlaps at least a portion of each silicon layer; and a plurality of oxide layers disposed between the pluralities of silicon-nitride and silicon layers, each oxide layer creating a separation spacing between each silicon-nitride and each silicon layers; wherein, when an optical signal is launched through the integrated waveguide polarizer, the optical signal is transitioned between each silicon-nitride layer and each silicon layer.

Abstract: An integrated photonics chip comprising: a plurality of optical channels extending a length of the integrated photonics chip; at least one variable optical attenuator (VOA) being optically connected to one of the plurality of optical channels, the at least one VOA comprising a silicon diode; at least one modulator being optically connected to another of the plurality of optical channels, the at least one modulator comprising a silicon diode; wherein the silicon diodes of the at least one VOA and the at least one modulator are adapted to receive biasing voltages; and wherein an application of the biasing voltages causes the silicon diodes of the at least one VOA and the at least one modulator to be reverse-biased, such that the at least one VOA and the at least one modulator are each adapted to detect a photocurrent of an optical signal being propagated along the plurality of optical channels.

Abstract: An integrated Mach-Zehnder Interferometer comprising: an upper arm and a lower arm; and a differential thermo-optic phase shifter comprising a first heating element and a second heating element collocated with the upper arm and the lower arm, respectively, the first heating element having a first resistance and the second heating element having a second resistance, an upper pad electrically connected to the first heating element, the upper pad being adapted to receive a first voltage, a lower pad electrically connected to the second heating element, the lower pad being adapted to receive a second voltage, and a common pad electrically connected to the first heating element and the second heating element, the common pad being adapted to receive a third voltage; wherein, when the first, the second, and the third voltages are applied to the upper, the lower, and the common pads, respectively, a phase shift difference is thermally produced.

Abstract: The present invention provides an apparatus to actively balance the thermal performance of paralleled power devices, comprising: a monitoring unit for monitoring the temperature of each power device of the paralleled power devices to judge whether the temperature is out of balance; and a balancing unit for adjusting power loss of the power devices with monitored higher temperatures so as to achieve the balance of the thermal performance of the paralleled power devices.

Abstract: An integrated transmitter chip comprising: at least one input port disposed at a first end; a first variable power divider optically connected to a first input port of the at least one input port, the first variable power divider being tunable to a first splitting ratio; a second and a third variable power dividers each optically connected to the first variable power divider, the second and the third variable power dividers being tunable to a second and a third splitting ratios; and a first and a second optical channels being optically branched from the second variable power divider, and a third and a fourth optical channels being optically branched from the third variable power divider; wherein an optical signal being launched into the first input port and having an input power is caused to be split by the first variable power divider into a first and a second optical signals.

Abstract: A system for optically aligning a photonics die to a fiber array, the fiber array comprising a first and a second fiber channels, the system comprising: the photonics die having: a first and a second optical channels; a first and a second wavelength division multiplexing (WDM) couplers each comprising a bar port, a cross port, and a common port, the first and the second WDM couplers being optically connected to the first and the second optical channels, respectively, via the bar ports and the common ports; and a waveguide crossing optically connecting the cross ports of the first and the second WDM couplers; the system being adapted to couple an optical signal received from the first fiber channel into the cross port of the first WDM coupler and into the waveguide crossing, the optical signal being propagated from the waveguide crossing into the cross port of the second WDM coupler.

Abstract: A method and system for locking the resonance frequency of ring resonators by using laser sources to emit a plurality of different wavelengths, applying a tagging signal to each of the wavelengths, multiplexing the tagged wavelengths using a wavelength division multiplexor, coupling the multiplexed tagged wavelengths onto a bus waveguide, detecting the multiplexed tagged wavelengths with a first photodetector disposed before a first ring resonator and a second photodetector disposed after a last ring resonator of a plurality of ring resonators, sending the signals detected by the first and second photodetector to a processor, which identifies and processes the tagging signals, generating a control signal for each ring resonator, by the processor and applying the control signals to phase shifters on each ring resonator of the plurality of ring resonators to tune and align the resonance wavelengths of the ring resonators with the wavelengths of the corresponding laser sources.

Abstract: The present invention provides a temperature protective device for a filter capacitor bank. The capacitor bank comprises two or more capacitors which are arranged in an array manner. The temperature protective device comprises a temperature measurement device which comprises: a cover body covering the capacitor bank; a single temperature sensor fixed at a center area of the cover body, which is used for measuring a temperature value of the capacitor bank; and a heat conduction pad located between the cover body and the capacitor bank, wherein the heat conduction pad and the cover body have fitted shapes. The temperature protective device of the present invention saves cost and can accurately realize temperature protection of the capacitor bank.

Abstract: The utility model provides a tower UPS frame and a tower UPS. The tower UPS frame comprises: a power supply module frame, which comprises two ports disposed oppositely; a power supply distribution frame; and a fan assembly, which comprises a fan frame and a fan fixed on the fan frame, wherein the power supply distribution frame and the fan frame are arranged in a same row as the power supply module frame and are detachably connected with the two ports of the power supply module frame. The tower UPS frame of the utility model is convenient in assembly and disassembly and reduces repair cost.

Abstract: The present invention provides a power factor correction circuit (21, 22), a power factor correction assembly (2) and an on-line uninterruptible power supply including the same. The power factor correction circuit (21) comprises a pulse width modulated rectifier (211, 221) and an isolated DC-DC converter (212, 222), wherein an output of the pulse width modulated rectifier (211, 221) is connected to an input of the isolated DC-DC converter (212, 222). The power factor correction assembly (2) comprises a plurality of power factor correction circuits (21, 22) described above, wherein inputs of pulse width modulated rectifiers (211, 221) in the plurality of power factor correction circuits (21, 22) are connected in series, and outputs of isolated DC-DC converters (212, 222) in the plurality of power factor correction circuits (21, 22) are connected in parallel.

Abstract: A method for fabricating a photonic integrated circuit (PIC) comprises providing a silicon-on-insulator (SOI) wafer comprising an insulator layer disposed between a base semiconductor layer and a SOI layer, wherein the SOI layer comprises a waveguide, providing at least one slot within the SOI layer, wherein the at least one slot is positioned on the same or opposite sides of the waveguide, and wherein the at least one slot is positioned at a predetermined distance away from the waveguide, and removing a portion of the insulator layer to form an etched-out portion of the insulator layer, wherein the etched-out portion is positioned directly beneath the waveguide, and wherein a width of the etched-out portion is at least the width of the waveguide.

Abstract: A method for fabricating a photonic integrated circuit (PIC) comprises providing a silicon-on-insulator (SOI) wafer comprising an insulator layer disposed between a base semiconductor layer and a SOI layer, wherein the SOI layer comprises a waveguide, providing at least one slot within the SOI layer, wherein the at least one slot is positioned on the same or opposite sides of the waveguide, and wherein the at least one slot is positioned at a predetermined distance away from the waveguide, and removing a portion of the insulator layer to form an etched-out portion of the insulator layer, wherein the etched-out portion is positioned directly beneath the waveguide, and wherein a width of the etched-out portion is at least the width of the waveguide

Abstract: An optical transceiver comprising an optical signal input, a first modulation section coupled to the optical signal input, a second modulation section coupled to the optical signal input and positioned in serial with the first modulation section, wherein the first modulation section comprises a first digital electrical signal input, a first digital driver coupled to the first digital electrical signal input, and a first modulator coupled to the first digital driver, and wherein the second modulation section comprises a second digital electrical signal input, a second digital driver coupled to the second digital electrical signal input, and a second modulator coupled to the second digital driver, and an optical signal output coupled to the first modulation section and the second modulation section.

Abstract: An optical modulator comprises a silicon substrate, a buried oxide (BOX) layer disposed on top of the silicon substrate, and a ridge waveguide disposed on top of the BOX layer and comprising a first n-type silicon (n-Si) slab, a first gate oxide layer coupled to the first n-Si slab, a first p-type silicon (p-Si) slab coupled to the first gate oxide layer, and a light propagation path that travels sequentially through the first n-Si slab, the first gate oxide layer, and the first p-Si slab.

Abstract: A metal-oxide semiconductor (MOS) optical modulator including a doped semiconductor layer having a waveguide structure, a dielectric layer disposed over the waveguide structure of the doped semiconductor layer, a gate region disposed over the dielectric layer, wherein the gate region comprises a transparent electrically conductive material having a refractive index lower than that of silicon, and a metal contact disposed over the gate region. The metal contact, the gate region, and the waveguide structure of the doped semiconductor layer may be vertically aligned with each other.

Abstract: An apparatus comprises a substrate comprising a silicon dioxide (SiO2) material disposed on top of the substrate, a silicon waveguide comprising a first adiabatic tapering and enclosed in the silicon dioxide material, and a low-index waveguide disposed on top of the substrate and adjacent to the first adiabatic tapering. A mode converter fabrication method comprises obtaining a mode converter comprising a substrate, a silicon waveguide disposed on the substrate and comprising a sidewall and a first adiabatic tapering, and a hard mask disposed on the silicon waveguide and comprising a silicon dioxide layer, wherein the hard mask does not cover the sidewall, and oxidizing the silicon waveguide and the hard mask, wherein oxidizing the silicon waveguide and the hard mask encloses the silicon waveguide within the silicon dioxide layer.

Abstract: An optical modulator comprises a silicon substrate, a buried oxide (BOX) layer disposed on top of the silicon substrate, and a ridge waveguide disposed on top of the BOX layer and comprising a first n-type silicon (n-Si) slab, a first gate oxide layer coupled to the first n-Si slab, a first p-type silicon (p-Si) slab coupled to the first gate oxide layer, and a light propagation path that travels sequentially through the first n-Si slab, the first gate oxide layer, and the first p-Si slab.

Abstract: An apparatus comprises a substrate comprising a silicon dioxide (SiO2) material disposed on top of the substrate, a silicon waveguide comprising a first adiabatic tapering and enclosed in the silicon dioxide material, and a low-index waveguide disposed on top of the substrate and adjacent to the first adiabatic tapering. A mode converter fabrication method comprises obtaining a mode converter comprising a substrate, a silicon waveguide disposed on the substrate and comprising a sidewall and a first adiabatic tapering, and a hard mask disposed on the silicon waveguide and comprising a silicon dioxide layer, wherein the hard mask does not cover the sidewall, and oxidizing the silicon waveguide and the hard mask, wherein oxidizing the silicon waveguide and the hard mask encloses the silicon waveguide within the silicon dioxide layer.

Abstract: An apparatus comprises a substrate comprising a silicon dioxide (SiO2) material disposed on top of the substrate, a silicon waveguide comprising a first adiabatic tapering and enclosed in the silicon dioxide material, and a low-index waveguide disposed on top of the substrate and adjacent to the first adiabatic tapering. A mode converter fabrication method comprises obtaining a mode converter comprising a substrate, a silicon waveguide disposed on the substrate and comprising a sidewall and a first adiabatic tapering, and a hard mask disposed on the silicon waveguide and comprising a silicon dioxide (SiO2) layer, wherein the hard mask does not cover the sidewall, and oxidizing the silicon waveguide and the hard mask, wherein oxidizing the silicon waveguide and the hard mask encloses the silicon waveguide within the silicon dioxide layer.

Abstract: An optical modulator comprises a silicon substrate, a buried oxide (BOX) layer disposed on top of the silicon substrate, and a ridge waveguide disposed on top of the BOX layer and comprising a first n-type silicon (n-Si) slab, a first gate oxide layer coupled to the first n-Si slab, a first p-type silicon (p-Si) slab coupled to the first gate oxide layer, and a light propagation path that travels sequentially through the first n-Si slab, the first gate oxide layer, and the first p-Si slab.